Is M0 core Bit banding capable?

[lpcware]

Content originally posted in LPCWare by rui.araujo on Fri Jun 13 04:12:24 MST 2014
I want to implement semaphores between the two cores using the bit banding region and the AHB  SRAM sections.

My implementation works fine on the M4 core but it hards fault while accessing the alias region on the M0.

is the M0 capable of bit banding on the LPC43xx?

If not, how should I implement semaphores between the two cores?

[lpcware]

Content originally posted in LPCWare by rocketdawg on Fri Jun 13 09:25:08 MST 2014
and M0 & M0+ cores do not have bit banding  (although ARM says it can be added in some cases)

[lpcware]

Content originally posted in LPCWare by TheFallGuy on Fri Jun 13 04:40:39 MST 2014
There is a whole section in the UM10503 on inter process communication. See Chapter 2.