There is no resource in SGPIO that would allow to synchronize to an I2S master. However, it is easily possible with the assistance of the SCT.
The idea is for SCT to monitor the internal state of the I2S slices, and gate the bit clock while SGPIO slices and the external I2S master are out of sync. The I2S bit clock goes to SGPIO, the I2S word select goes to SCT, and an external connection is required from an SCT output to an SGPIO pin to provide the clock qualifier function.
An SGPIO slice (slice J, SGPIO3) is configured to provide its own idea of the WS signal. It is connected to CTIN_0 of the SCT via the GIMA. A falling edge of the signal causes SCT to gate the SGPIO bit clock ("CLOCK_GATE"=0). SGPIO slices are now freezed in a known state. SCT monitors the master's WS signal, and reenables the bit clock ("CLOCK_GATE"=1) when it sees a falling edge there. Master and slave are now in sync, and the screenshot shows that no further clock gating occurs in the following frames. Synchronization only took one frame time.
The attached initialization file is not a complete project, but I hope you can get the idea from it. Data transfer is done in the SGPIO interrupt, and includes extracting the 24-bit samples (also the bit flipping due to SGPIO sending LSB first only).
Only two events are used in SCT, but two pins have to be used for connecting SCT to SGPIO.
There is no resource in SGPIO that would allow to synchronize to an I2S master. However, it is easily possible with the assistance of the SCT.
The idea is for SCT to monitor the internal state of the I2S slices, and gate the bit clock while SGPIO slices and the external I2S master are out of sync. The I2S bit clock goes to SGPIO, the I2S word select goes to SCT, and an external connection is required from an SCT output to an SGPIO pin to provide the clock qualifier function.
An SGPIO slice (slice J, SGPIO3) is configured to provide its own idea of the WS signal. It is connected to CTIN_0 of the SCT via the GIMA. A falling edge of the signal causes SCT to gate the SGPIO bit clock ("CLOCK_GATE"=0). SGPIO slices are now freezed in a known state. SCT monitors the master's WS signal, and reenables the bit clock ("CLOCK_GATE"=1) when it sees a falling edge there. Master and slave are now in sync, and the screenshot shows that no further clock gating occurs in the following frames. Synchronization only took one frame time.
The attached initialization file is not a complete project, but I hope you can get the idea from it. Data transfer is done in the SGPIO interrupt, and includes extracting the 24-bit samples (also the bit flipping due to SGPIO sending LSB first only).
Only two events are used in SCT, but two pins have to be used for connecting SCT to SGPIO.
