I2S @ 192kHz

[andrew_lonsdale]

Can the LPC546XX series (LPC54608 specifically) support 192kHz I2S operation for 16bit stereo samples.

I think that the equations in the user manual suggest it can, but the text stops short of quoting support for 192kHz audio. It states "16, 22.05, 32, 44.1, 48, and 96 kHz, and others.". Other devices in the LPC range (i.e. LPC4330) quote support for 192kHz explicitly.

The SCLK required would be 6.144MHz from an MCLK of 24.576MHz which is in line with normal practice and the 96kHz/32bit example in the user manual.

Is there some other limitation that I'm not seeing that tops the operation at 96kHz?

Kind regards

Charles

[andrew_lonsdale]

Soledad, Sean Zhou,

Many thanks for your responses. It is kind that you took the time.

I am currently trying to select a microcontroller for a new design, and need to do so with some certainty before I spend the time developing a board and software. So I'm afraid I don't have anything that I can try on the bench.

I just find the comments in the data sheet strange, in that NXP state 96kHz as and example but not 192kHz. In other datasheets, they have specifically indicated 192kHz support. I'm concerned that there may be a technical restriction.

I will try and dig a little further and will report if I find anything else.

Once again, thanks for your help.

Regards

Andrew

[andrew_lonsdale]

I now have the board and can confirm that the I2S is working at 192kHz.

[seanzhou]

Hi,

In your condition, MCLK clock source is from AUDIO PLL 24.576MHz and SCK is 6.144MHz. That's mean sampling 4 times per SCK clock. What if sampling 2 times per SCK clock?

If it is work on 12.288MHz SCK, sample rate should be 12.288MHz/(32bit*2channel) = 192KHz.

Maybe you can try this, and share your test result. Thank you. 

[soledad]

Hi, 

Sampling frequencies supported depends on the specific device configuration and applications constraints (for example, system clock frequency and PLL availability.) but generally supports standard audio data rates.

Be aware that the Flexcomm Interface function clock frequency should not be above 48 MHz. 

Regards

Sol