Why is LPC546xx Flash Controller Undocumented?

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Why is LPC546xx Flash Controller Undocumented?

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trchen1033
Contributor I

The user manual UM10912 doesn't have anything about the programming model of the flash controller on LPC546xx, and the SDK driver simply uses the IAP provided by the boot ROM API. It doesn't feel like a simple omission of information, more like intentionally concealed. For example PDRUNCFG0[5] is assigned to power down the flash controller, but is shown as a reserved bit in the manual.

While we appreciate the boot ROM API offered the IAP since the driver can't run off the flash anyway, however, there are limitation to the boot ROM API. For example it cannot be used with a DMA channel, or use interrupt instead of polling to reduce CPU load, also it is unknown whether it is safe to use with preemptive multithread OS.

There are also other low-level aspect that may be useful to developers, for example the exact ECC matrix and the bit pattern that can be over-programmed.

Is there a specific reason why the programming model has to be kept secret from developers?

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trchen1033
Contributor I

All the Flash related configurations for user design are documented in UM. Users can refer it for their design without problem.

Perhaps I overlooked it. Could you please point out which chapter in the UM the programming model of the flash controller is documented?

You said "PDRUNCFG0[5] is assigned to power down the flash controller". How do you state this?  From UM, This bit is reserved.

Yes I did say in the UM the bit is documented as reserved, but if you traced the boot ROM API with a debugger, the bit is checked prior to any flash operations. I don't know if it in fact power down the flash controller, but it is definitely not reserved for future use. Perhaps reserved for internal use? Anyway this is exactly why I claim the UM is concealing information from developers.

 

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ZhangJennie
NXP TechSupport
NXP TechSupport

Hi

Besides the Flash Power Control bits I mentioned in my previous snapshot, you can check UM Chapter 42: LPC546xx Flash signature generator. This chapter includes description of Flash control registers.

For users,I can confirm PDRUNCFG0[5]  is reserved. If this bit make trouble to your application function, please let us know what problem it results in.


Have a great day,
Jun Zhang

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trchen1033
Contributor I

UM Chapter 42 describes the flash signature generator, which implements some sort of CRC algorithm, and has nothing to do with basic flash operations. It didn't answer my original question, why the UM doesn't document the flash controller but forces the developers to use boot ROM IAP instead? Is the omission intentional? There are applications that need to reprogram flash while calling into the boot ROM being inappropriate.

I understand there might be legit reason why you can't document the flash controller, e.g. licensed from a third-party. I just want to make sure the omission is not a trivial mistake. Of course it would be nice if you could explain why it couldn't be documented if it's intentional.

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bernhardfink
NXP Employee
NXP Employee

In all the history of LPC microcontrollers I don't see it differently: the flash controller itself and the way the flash is erased and programmed is mostly described over the IAP API. The few static settings like wait states or the CRC feature are explained.

I have no problem with the expression "Reserved: leave existing value unchanged", it exactly defines the usage of this bit field. It doesn't define it "for future use" and it doesn't express that it is not used by the system. It only says that the user should not touch the existing values.

We implicitely described the bit PDRUNCFG0[5] by opening up the power lib source code

https://www.nxp.com/docs/en/application-note/TN00038.zip 

where you find the definition of this bit and the usage for achieving lowest power operation. See further down below why we don't document it this way in the UM.

With regards to the missing description of the flash controller itself: it is a proprietary flash architecture and we don't want to open it up. As this flash is always part of the LPC microcontroller device, there is even no need to do that, because the operation is handled by the ROM code API. This is as good as the programming procedures defined for external flash devices.

The reason behind the reduction to API usage is simple:  minimize the risk of doing something wrong.

I can't think of applications where calling into the boot ROM is inappropriate. By doing this, you only need to consider a few things:

  • Active interrupts are risky, as they would interrupt and delay activities which have been triggered to run from ROM
  • For activities on the flash the interrupts are dangerous, as the interrupt vectors reside at the beginning of the flash. During erase and program cycles the flash goes offline from the bus and any access from the ARM to the interrupt vector table would cause an exception. But it would not be an organized exception, as the vector the ARM gets back for the location of the exception handler is random ...
    To work around this problem, you can remap the interrupt vector table to another memory location, for example to RAM. Then your application can continue with its job, under the condition that any access to flash memory locations is forbidden.

Regards,

Bernhard.

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ZhangJennie
NXP TechSupport
NXP TechSupport

Hi Tien-Ren Chen

Flash controller is only for Flash Writing.

All the Flash related configurations for user design are documented in UM. Users can refer it for their design without problem.

You said "PDRUNCFG0[5] is assigned to power down the flash controller". How do you state this?  From UM, This bit is reserved.  Flash  power control only has these two registers:

pastedImage_1.png

For DMA usage, see Chapter 15: LPC546xx DMA controller


Have a great day,
Jun Zhang

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