How to clear the System FIFO transmit

[chrisoneill]

Using the 54102 with the System FIFO connected to a SPI peripheral.  Each transaction leaves a few extra bytes in the transmit FIFO, want to clear before the next transaction.  Set the TXFLUSH bit in the CTLSETSPI register, then TXFLUSHCLR bit in CTLCLRSPI register.  TXCOUNT doesn't change and the extra bytes are transmitted out in the next SPI operation.

[Alexis_A]

Hi Chris,

In which moment are you flushing the FIFO? I think it you would need to stop the transmission and reception first to not interfere with the flush of the FIFO, also, if you have the interruption enabled could be useful to dissable it before.

Let me know if this helps you.

Best Regards,

Alexis Andalon