Since there are 2 cores in LPC54114, I want to know how the M4 boot the M0 core in the chip. Every documents I found did not say anything specifically about this step.
Besides, I am using LPCOpen library, when I try to open the function:
Chip_CPU_CM0Boot( uint32_t *coentry uint32_t *costackptr)
I can only find the declaration in the header file. I don't know its implementation. Where can I find it?
Solved! Go to Solution.
Hi Chen,
Chip_CPU_CM0Boot() is defined in library file syscon_5411x.c. The function of it is to setup M0+ boot (Set up M0+ stack and boot location) and reset M0+ core. I extract them as below:
/* Setup M0+ boot and reset M0+ core */
void Chip_CPU_CM0Boot(uint32_t *coentry, uint32_t *costackptr)
{
#define M0_STACK_REG (*(volatile uint32_t *)
uint32_t temp;
/* Setup M0+ stack and M0+ boot location */
LPC_SYSCON->CPSTACK = (uint32_t) costackptr;
LPC_SYSCON->CPBOOT = (uint32_t) coentry;
temp = LPC_SYSCON->CPUCTRL | CPUCTRL_SETMASK | MC_CM0_CLK_ENABLE;
/* Enable M0+ clocking with reset asserted */
LPC_SYSCON->CPUCTRL = temp | MC_CM0_RESET_ENABLE;
/* De-assert reset on M0+ */
LPC_SYSCON->CPUCTRL = temp;
}
Have a great day,
Jun Zhang
-------------------------------------------------------------------------------
Note:
- If this post answers your question, please click the "Mark Correct" button. Thank you!
- We are following threads for 7 weeks after the last post, later replies are ignored
Please open a new thread and refer to the closed one, if you have a related question at a later point in time.
-------------------------------------------------------------------------------
Hi Chen,
What do you mean "wake up M0+ core"? do you mean boot M0+ core from M4 core ?
or
M0+ core is in low power mode, you need wake it up?
Have a nice day,
Jun Zhang
I mean boot M0+ core. I've change the description of the question. Thx.
Hi Chen,
Chip_CPU_CM0Boot() is defined in library file syscon_5411x.c. The function of it is to setup M0+ boot (Set up M0+ stack and boot location) and reset M0+ core. I extract them as below:
/* Setup M0+ boot and reset M0+ core */
void Chip_CPU_CM0Boot(uint32_t *coentry, uint32_t *costackptr)
{
#define M0_STACK_REG (*(volatile uint32_t *)
uint32_t temp;
/* Setup M0+ stack and M0+ boot location */
LPC_SYSCON->CPSTACK = (uint32_t) costackptr;
LPC_SYSCON->CPBOOT = (uint32_t) coentry;
temp = LPC_SYSCON->CPUCTRL | CPUCTRL_SETMASK | MC_CM0_CLK_ENABLE;
/* Enable M0+ clocking with reset asserted */
LPC_SYSCON->CPUCTRL = temp | MC_CM0_RESET_ENABLE;
/* De-assert reset on M0+ */
LPC_SYSCON->CPUCTRL = temp;
}
Have a great day,
Jun Zhang
-------------------------------------------------------------------------------
Note:
- If this post answers your question, please click the "Mark Correct" button. Thank you!
- We are following threads for 7 weeks after the last post, later replies are ignored
Please open a new thread and refer to the closed one, if you have a related question at a later point in time.
-------------------------------------------------------------------------------