EXT_SYNC polarity and timing requirements

[JPE]

Hi,

I have searched the Data Sheet and Reference Manual of the LPC553x without finding any information about the the polarity and timing requirements for the "EXT_SYNC" signal when using it for an external synchronization of the PWM module.

Should the signal on the EXT_SYNC pin be "High" under normal conditions and "Low" to trigger the synchronization?

What is the minimum pulse length of the EXT_SYNC-pulse?

When is the reinitialization of the PWM counter actually performed, a defined time after the "High" to "Low"-edge or at the "Low" to "High" edge of the EXT_SYNC-pulse?

Kind regards
Jörn

[Habib_MS]

Hello @JPE,

I highly recommend reviewing Chapter counter synchronization of Application Note AN14196, available on this page, for detailed information regarding EXT_SYNC and counter synchronization. Although this application note is specifically designed for the MCX N Series, it serves as a valuable reference for understanding FlexPWM, which is also utilized in this context.

BR
Habib

[JPE]

Hi Habib!

Thank you very much for your response, but the AN you are referring to doesn't really answer my questions.

I've been using the FlexPWM module on several platforms for a couple of years, but so far we have never been using an external trigger for the PWM synchronization.
Therefore I'm in doubt of the physical shape of the signal (polarity, timing, trigger point).

My assumption is, that the PWM synchronization will be performed when there is a rising edge on the pin assigned as the EXT_SYNC signal.
I would also assume that there is some kind of filter on the pins so the signal has to be stable for a few cycles before and after the edge.

I actually also asked ChatGPT, which confirmed my assumptions with the following answers:

• The synchronization is performed when the EXT_SYNC pulse is seen/asserted (rising edge) and sampled by the PWM logic — i.e. the counter is reinitialized when the sync input asserts (and is captured by the peripheral’s synchronizer). Put simply: a low→high (rising) transition is the normal trigger. (NXP Semiconductors)
• NXP does not document a single fixed “minimum pulse width” for EXT_SYNC in the LPC553x documents. The peripheral samples/synchronizes external control signals to the IPBus/peripheral clock, so you must supply a pulse long enough to survive input synchronizers and any pin filtering. In practice design for ≥ 1–3 IPBus clock cycles (preferably 3); if your IPBus/peripheral clock is 100 MHz that means ≥ 10–30 ns recommended. If you have pin filters / external RCs or long traces, increase the pulse width accordingly (µs scale for slow signals). (mcuxpresso.nxp.com, NXP Semiconductors)

However, I wasn't able to get these statements verified in the documents that ChatGPT is referring to (for example AN4485, which seems to be using the same FlexPWM module as the MCX N you were referring to).

Therefore I was hoping to get some additional information here that wasn't available in the application notes and reference manuals.

BR. Jörn

[Habib_MS · Accepted solution]

Hello @JPE,

There is not a dedicated application note that outlines the EXT_SYNC requirements specifically. However, you can refer to AN12200, which demonstrates the use of EXT_SYNC, as highlighted in this community post by _Leo_. Although AN12200 focuses on eFlexPWM, its implementation can still serve as a useful reference for FlexPWM configurations.

Also, I can suggest review these community post that could be helpful:

EXT_SYNC of PWM initial frequency settings - NXP Community

Difference between FlexPWM FORCE_OUT and EXT_SYNC - NXP Community
BR
Habib

[JPE]

Hello Habib,

thank you for the additional references.

We're actually also using the eFlexPWM module, so it should be possible to use the according info directly.

BR. Jörn