Connection and setup of 4-wire I2S on LPC4337?

[moller]

As the title states, I need to connect a stereo CODEC in a 4-wire configuration. Mostly I see the UDA1380 CODEC being used but since this is obsolete I am going for the NAU8822LYG. This CODEC has 5 I2S pins:

MCLK (Master Clock)

BCLK (bit/data clock)
FS (Frame Sync / Word Select)

DACIN (Data In)

and

ADCOUT (Data Out)

(for now I have done the following:

I2S0_TX_MCLK -> MCLK

I2S0_TX_SCK -> BCLK

I2S0_TX_WS -> FS

I2S0_TX_SDA -> DACIN

I2S0RXSDA -> ADCOUT)

How would I connect this to the LPC4337? Furthermore, does anyone have example code to make this work? the UM10503 manual makes no sense to be how how go about this task. When they talk about the 4-wire setups I can not tell how I actualyl connect this to my CODEC. 

Thanks in advance

[bernhardfink · Accepted solution]

We had this topic already more than a month ago, right?

You're wiring looks good. You only need to set the registers correctly.

You need to consider the following:  MCLK does not necessarily belong to the I2S interface. It is the system clock for the audio codec, according to the NAU8812 data sheet it can be any clock between 8MHz and 33MHz. So when the User Manual talks about 4-wire interface, then it's the 4 wires SCK / WS / RX_SDA / TX_SDA.

Having the MCLK on top in phase with these signals is maybe a good option, so providing it from the LPC4300 side is for sure the best solution. Using the audio PLL inside the LPC4300, you can already generate a suitable system clock for the codec and you don't need to use the fractional PLL from the NAU8812.

The UDA1380 could work with this MCLK as well, but has also the option to generate its own system clock with a PLL, based on the FrameSync clock input.

The question is now whether you need to realize input/output or only output. The so called 4-wire mode is the minimum setup for an RX/TX interface. If you also supply MCLK to the codec then this is the fifths wire.

Let's assume the LPC4300 is the I2S master and you use RX/TX in the 4-wire mode:

• You need 4 signals:  TX / RX / SCK / WS
• The WS signal is used for framing both RX and TX data, both are bit-sampled with the SCK signal
• We can decide to use TX_SCK and TX_WS as timing signals, but RX_SCK and RX_WS is an option as well. This makes it maybe so complex to understand. The transmitter and the receiver could work independently from each other, each with own SCK and WS signals. They could work even with a different format. But in most setups you don't need this, the transmitter and the receiver should use the same timing anf the format for RX/TX is thew same, so settings in register DAO and DAI are the same.
• If you look to the discrete figures 152 and 159 you might not see the greater context
• When you go to Fig. 147 where all 8 pins are shown, you simply remove either pins I2S_TX_MCLK / I2S_TX_SCK / I2S_TX_WS  or  I2S_RX_MCLK / I2S_RX_SCK / I2S_RX_WS and take care that the register settings in DAO / DAI / TXMODE / RXMODE are correct for your setup.
• You operate the I2S0 interface as master (for both transmitter and receiver), so the timing SCK and WS comes from the LPC4300. You supply these two signals to the codec and you use these signals inside the LPC4300 to transmit data and to receive data.

Hope this helps a little bit.

[moller]

This was exactly what I was looking for. It is a perfect explanation of how to understand this correctly. I am thanking you a lot for the patience and superb description!

Kind regards