Hello NXP,
I want to clarify a few things regarding the SGPIO for LPC 43XX.
- When using the slice mux cfg register, is there a way to invert the external input clock?
- When using a qualifier for sgpio mux cfg register, is there a way to only use it once on a periodic signal? This means, we only want to use the qualifier on the first detection of an input slice.
3. We have a loopback set-up in our board. SGPIO 8 serves as a clock input of SGPIO 0 and SGPIO 1. SGPIO 10 serves as data input to SGPIO 1. We set-up the slice corresponding to SGPIO 1 clk capture mode to use the rising clock edge, so that we can save the data at the falling edge. However, for some reason, this behavior is not seen in my tests on my board. The performance varies between runs.
