Hello David
Thanks for your support
In my application I’m using FRCDIV and LIRC_DIV2 to get low PWM Duty Cycle.
By doing few experiments with FRCDIV and LIRC_DIV2 setup, I found that if total division is greater than 128 x 2 or 2 x 128 I can’t read FlexIO registers.
I tried this on flexio_pwm_frdmkl43z demo and my bare-metal test.
In my test I have used KExTools v2 for pin_mux and clock_config generation.
I have also replaced the flexio_pwm.c with my code I got same behavior.
Is there any restriction on total division generated by FRCDIV and LIRC_DIV2?
Regards
Shaul