Hi kerryzhou,
Thanks for sharing the relevant portions from the Reference Manual.
From the snapshots of the reference manual, does it imply that only the ADACK needs to meet the specifications, and there is no such restrictions in case bus clock is used as the input clock?
I am planning on using the bus clock, and will be trying with the below options:
Can you please validate my calculations below:
OPTION 1: Bus clock (48 MHz) with no divider, fastest conversion
ADCx_CFG1[ADICLK] set to 0(dec). Input clock set to bus clock
ADCx_CFG1[ADIV] set to 0(dec). Divide ratio is 1
I assume ADCK gets set to 48 MHz
OPTION 2: Bus clock(48 MHz)/2 with max. divider, slowest conversion
ADCx_CFG1[ADICLK] set to 1(dec). Input clock set to bus clock/2
ADCx_CFG1[ADIV] set to 3(dec). Divide ratio is set to 8
I assume ADCK gets set to 3 MHz
I have another query regarding the conversion time calculation, but I will create a separate query for that
Thanks