What is the IO buffer propagation delay for K61 MCU?

[sing-yew_chan]

Hi all,

Now I am studying the write and read timing of the DDR controller including the timing of DDR signals through the DDR PHY interface. As far as I know, the read and write timing in PHY interface can be controlled through the DDR registers. However, I cannot justify the timing of the PHY interface with the missing piece of DDR IO buffer propagation delay of the K61 MCU with part number of MK61FN1M0VMJ15.

For example, based on the datasheet for NXP IMX50 with the link to the datasheet below,

https://www.nxp.com/docs/pcn_attachments/15805_IMX50CEC.pdf 

The DDR IO buffer propagation delay is given (pg 47),

Hope that anyone of you guys can help to provide the IO buffer propagation delay of the K61 MCU.

Thank you very much.

Regards,

Jason 

[FelipeGarcia]

Hi Jason,

Unfortunately, we do not have the timing at that very detailed level. Instead, the datasheet contains the “output valid” specification which covers the timing specifications of the DDR controller in regards to the external signals.

Best regards,

Felipe

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