Watchdog Interrupt not reached, Cortex M4, mqx KSDK

[_ZZ_]

Hello everybody, 

this is my second question on watchdog of Kinetis MCUs. 

I have been working on this for a while now and I can't get my head around it. I am using a Cortex M4 K20 micro for my application. I have managed to configure the watchdog successfully and it is working fine. but if the watchdog is not kicked on time it does not seem to be executing its interrupt service routine before doing the reset. my watchdog configuration is 100% right, I have even tried the KSDK drivers to do the configuration. none of them seem to be executing the watchdog isr.

I did everything I could to find out whether this isr is executed or not. 

I did a lot of research online, some -people say, it is not possible to put break point inside the watchdog isr. 

does anybody have an example of kinetis watchdog with interrupt enabled which has been tested and works for sure.   

many thanks for any response,

Roosbeh

[mjbcswitzerland]

Roosbeh

The uTasker project includes verified code for the watchdog interrupt handler for all watchdog types that support it (including the one in the K20 - reference below).

1. Initialisation:

UNLOCK_WDOG();
WDOG_TOVALL = (2000/5);

WDOG_TOVALH = 0;
WDOG_STCTRLH = (WDOG_STCTRLH_STNDBYEN | WDOG_STCTRLH_WAITEN | WDOG_STCTRLH_STOPEN | WDOG_STCTRLH_WDOGEN | WDOG_STCTRLH_IRQRSTEN) // watchdog enabled to generate reset on 2s timeout (no further updates allowed) with interrupt before reset takes pace

2. Enable interrupt in NVIC:

fnEnterInterrupt(irq_WDOG_ID, 0, wdog_irq);

3. Interrupt handler:

static void wdog_irq(void)
{
    WDOG_STCTRLL = (WDOG_STCTRLL_INTFLG | WDOG_STCTRLL_RES1);            // clear interrupt flag
    *BOOT_MAIL_BOX = 0x9876;                                             // set a pattern to the boot mailbox to show that the watchdog interrupt took place
}

After the reset the location BOOT_MAIL_BOX ( allocation in SRAM that is otherwise not used or initialised) will show the value has been set.

The interrupt handler only has a very short time (number of clocks) to operate before the reset unconditionally occurs and so breakpoints in the routine (or writing data to Flash) are not possible.

Regards

Mark

[_ZZ_]

Hi Mark,

thanks for your response, 

will I get enough time to save the content of the last stack frame somewhere inside a external RAM? or I would run of time time!

regards,

Roosbeh

[mjbcswitzerland]

Roosbeh

There are (if I remember correctly) 256 clocks between the watchdog interrupt and the reset so it depends on your code and its efficiency.

If this is not adequate, or you prefer saving more data ot to Flash consider using a HW timer/watchdog combination as described in this topic: https://community.nxp.com/thread/462210 

Regards

Mark

[_ZZ_]

Good morning, 

I tried the method you mentioned in your post and proved the the watchdog interrupt is reached for sure. I think I should come up with some inline assembly to write the stack frame to the external RAM. 

thank you, it was really helpful