USB Unknown Device Error

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USB Unknown Device Error

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danieldelatorre
Contributor IV

I'm having issues getting the MQX CDC Device example (i.e., virtual_comm) running on my custom board.  I'm simply trying to use our MCU's USB as a device in FS mode without OTG.  I'm able to get the code working with the k60f120 tower board just not with my custom hardware.  My MCU is the MK60FX512VLQ12 running with the following clock settings:

Core clock = 96 MHz

  1. Bus clock = 48 MHz
  2. External bus Clock = 48 MHz
  3. Flash Clock = 24 MHz

I'm using a 12 MHz crystal going into XTAL1 and EXTAL1 to generate all of the clocks.

My custom board and the k60f120 demo board are both running MQX 4.0.1 RTOS.  The next 2 screenshots are from processor expert where I have imported the BSP so that I could make changes, BTW I'm pretty confident that the BSP was ported into PE properly because I went through a long process to do so with the help from a freescale tech support.

There is more to read after the screenshots so please continue.

Untitled.png

Untitled2.png

The following 3 images are relevant screenshot from the schematic of my custom board.

Untitled3.png

One interesting thing to note is that we are configuring our device hardware to be a "self powered" device, i.e., we plug in our own 5 volts into the VREGIN and then use the internal USB regulator to power our chip by connecting Vout33 to the MCU's VDD.  The USB VREG module outputs up to 120 mA and at the moment we are well under 120 mA so I don't think that I'm at the maximum amount of output current.

Untitled4.png

The image below shows where USB DP and DM are being connected to the MCU.  Please note that we are currently not doing anything with the PTE12/USB_VBUS pin shown below.

Untitled5.png

The virtual_comm.c, virtual_comm.h, usb_descriptor.c, and the usb_descriptor.h have not really been changed at all.  The files were directly from Freescale's example and work just fine with the k60 tower just not with my custom board.  It is important to say that I do have 2 different BSP's when testing this.  One BSP is for the k60 tower and the other is for my custom hardware, but the application layer code is identical.  My application layer code is interfacing with the RTOS via the run time libraries.

Our USB signals are coming in properly so I don't think that we have our wiring anything wrong.  I have put a logic analyzer on USB0_DP and USB0_DM right before going into the MCU pins and I do see J,K, and SE0 signals coming in.

The exact error shown in windows can be seen in the screenshot shown below.

Untitled6.png

When I run the same code on the k60 tower the descriptor data goes across, which tells me it successfully enumerated.  The only error I get from windows is that the driver is missing, which is ok.

Untitled7.png

I have a few questions which could perhaps lead me to the answer:

1. Do I have to setup a particular pin for VBUS_detect?

2. If I'm using the USB module on my custom hardware as a self powered (i.e., vregin is always connected to my power supply and NOT VBUS) do I need to worry about setting up a pin for detecting vbus?

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danieldelatorre
Contributor IV

I finally figured out how to fix this.  For some reason you can't use MCGPLL0CLK as the USB clock source when you only have a 12 MHz crystal plugged into XTAL1...  In case you didn't read the entire history on this post, I had a different clock configuration than what is on the tower.  I have nothing connected to XTAL0 and a 12 MHz crystal connected to XTAL1, as appose to the tower where it has a 50 MHz clock in XTAL0 and a 12 MHz crystal in XTAL1.  What I ended up doing is configuring the BSP through processor expert to use PLL 1 and NOT PLL 0 and then changed around the _bsp_usb_io_init function, as seen in the code snippet below, to use MCGPLL1CLK for the USB.  Processor Expert does not update _bsp_usb_io_init if you change around the clock settings so you MUST be aware of this if you decide to deviate from the k60twr120 clock settings. So now PLL1  is going to be used as the MCG clock source for driving core, bus, external bus, and flash clock.  I still don't understand why I could not use MCGPLL0CLK because the clock diagram, mentioned in the previous posts, clearly makes it look like you can.  Anyways it works now so I'm happy.

As a note to freescale support, you guys should have processor expert automatically update the _bsp_usb_io_init code.

Untitled.png

_mqx_int _bsp_usb_io_init
(
    _mqx_uint dev_num
)
{
    if (dev_num == 0) {
#if PE_LDD_VERSION
        /* USB clock is configured using CPU component */

        /* Check if peripheral is not used by Processor Expert USB_LDD component */
        if (PE_PeripheralUsed((uint_32)USB0_BASE_PTR) == TRUE) {
            /* IO Device used by PE Component*/
            return IO_ERROR;
        }
#endif
/* Configure USB to be clocked from PLL1 */
        SIM_SOPT2_REG(SIM_BASE_PTR) &= ~(SIM_SOPT2_USBFSRC_MASK | SIM_SOPT2_PLLFLLSEL_MASK);
        SIM_SOPT2_REG(SIM_BASE_PTR) |= SIM_SOPT2_USBFSRC( 2 ) | SIM_SOPT2_PLLFLLSEL( 2 );
        /* Configure USB to be clocked from clock divider */
        SIM_SOPT2_REG(SIM_BASE_PTR) |= SIM_SOPT2_USBF_CLKSEL_MASK;
        /* Configure USB divider to be 120MHz * 2 / 5 = 48 MHz */
        SIM_CLKDIV2_REG(SIM_BASE_PTR) &= ~(SIM_CLKDIV2_USBFSDIV_MASK | SIM_CLKDIV2_USBFSFRAC_MASK);
        SIM_CLKDIV2_REG(SIM_BASE_PTR) |= SIM_CLKDIV2_USBFSDIV(4) | SIM_CLKDIV2_USBFSFRAC_MASK;

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danieldelatorre
Contributor IV

I finally figured out how to fix this.  For some reason you can't use MCGPLL0CLK as the USB clock source when you only have a 12 MHz crystal plugged into XTAL1...  In case you didn't read the entire history on this post, I had a different clock configuration than what is on the tower.  I have nothing connected to XTAL0 and a 12 MHz crystal connected to XTAL1, as appose to the tower where it has a 50 MHz clock in XTAL0 and a 12 MHz crystal in XTAL1.  What I ended up doing is configuring the BSP through processor expert to use PLL 1 and NOT PLL 0 and then changed around the _bsp_usb_io_init function, as seen in the code snippet below, to use MCGPLL1CLK for the USB.  Processor Expert does not update _bsp_usb_io_init if you change around the clock settings so you MUST be aware of this if you decide to deviate from the k60twr120 clock settings. So now PLL1  is going to be used as the MCG clock source for driving core, bus, external bus, and flash clock.  I still don't understand why I could not use MCGPLL0CLK because the clock diagram, mentioned in the previous posts, clearly makes it look like you can.  Anyways it works now so I'm happy.

As a note to freescale support, you guys should have processor expert automatically update the _bsp_usb_io_init code.

Untitled.png

_mqx_int _bsp_usb_io_init
(
    _mqx_uint dev_num
)
{
    if (dev_num == 0) {
#if PE_LDD_VERSION
        /* USB clock is configured using CPU component */

        /* Check if peripheral is not used by Processor Expert USB_LDD component */
        if (PE_PeripheralUsed((uint_32)USB0_BASE_PTR) == TRUE) {
            /* IO Device used by PE Component*/
            return IO_ERROR;
        }
#endif
/* Configure USB to be clocked from PLL1 */
        SIM_SOPT2_REG(SIM_BASE_PTR) &= ~(SIM_SOPT2_USBFSRC_MASK | SIM_SOPT2_PLLFLLSEL_MASK);
        SIM_SOPT2_REG(SIM_BASE_PTR) |= SIM_SOPT2_USBFSRC( 2 ) | SIM_SOPT2_PLLFLLSEL( 2 );
        /* Configure USB to be clocked from clock divider */
        SIM_SOPT2_REG(SIM_BASE_PTR) |= SIM_SOPT2_USBF_CLKSEL_MASK;
        /* Configure USB divider to be 120MHz * 2 / 5 = 48 MHz */
        SIM_CLKDIV2_REG(SIM_BASE_PTR) &= ~(SIM_CLKDIV2_USBFSDIV_MASK | SIM_CLKDIV2_USBFSFRAC_MASK);
        SIM_CLKDIV2_REG(SIM_BASE_PTR) |= SIM_CLKDIV2_USBFSDIV(4) | SIM_CLKDIV2_USBFSFRAC_MASK;

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danieldelatorre
Contributor IV

Yah, I already knew that...

Just that I'm curious as to why PE only offers those two options for that particular field.  I just want to make sure that deep down in the code there isn't a "disconnect" with how PE displays the settings and the actual generated code.  At this point I'm going to assume that MCGPLL0 is truly using oscillator 1...

Will someone else be able to help? I really needed this running yesterday and it is currently stopping all progress on this project.

BTW, I found 2 posts that were similar to my problem.  They are:

https://community.freescale.com/message/89074#89074

https://community.freescale.com/message/348157#348157

From the posts I figured out that Processor Expert doesn't modify MQX's USB device stack settings when changing the clock settings.  So, like the people is the previous posts I started to modify some registers and found out that the default settings where going off of MCGPLL0 with a core clock of 120 MHz.  Below is the code snippet where those clock settings can be found.  So I decided to go back to using the following settings:

core = 120 MHz

bus = 60 MHz

external bus = 40 MHz

Flash = 20 MHz

I'm still having the same problem, unfortunately, although I'm sticking with these clock settings for now sense these have worked in the past for the k60 tower board.

init_gpio.c

-------------------------------------------------------

_mqx_int _bsp_usb_io_init

(

    _mqx_uint dev_num

)

{

    if (dev_num == 0) {

#if PE_LDD_VERSION

        /* USB clock is configured using CPU component */

        /* Check if peripheral is not used by Processor Expert USB_LDD component */

         if (PE_PeripheralUsed((uint_32)USB0_BASE_PTR) == TRUE) {

             /* IO Device used by PE Component*/

             return IO_ERROR;

         }

#endif

/* Configure USB to be clocked from PLL0 */

        SIM_SOPT2_REG(SIM_BASE_PTR) &= ~(SIM_SOPT2_USBFSRC_MASK);

        SIM_SOPT2_REG(SIM_BASE_PTR) |= SIM_SOPT2_USBFSRC(1);

        /* Configure USB to be clocked from clock divider */

        SIM_SOPT2_REG(SIM_BASE_PTR) |= SIM_SOPT2_USBF_CLKSEL_MASK;

        /* Configure USB divider to be 120MHz * 2 / 5 = 48 MHz */

        SIM_CLKDIV2_REG(SIM_BASE_PTR) &= ~(SIM_CLKDIV2_USBFSDIV_MASK | SIM_CLKDIV2_USBFSFRAC_MASK);

        SIM_CLKDIV2_REG(SIM_BASE_PTR) |= SIM_CLKDIV2_USBFSDIV(4) | SIM_CLKDIV2_USBFSFRAC_MASK;

        /* Enable USB-OTG IP clocking */

        SIM_SCGC4_REG(SIM_BASE_PTR) |= SIM_SCGC4_USBFS_MASK;

        /* USB D+ and USB D- are standalone not multiplexed one-purpose pins */

        /* VREFIN for device is standalone not multiplexed one-purpose pin */

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danieldelatorre
Contributor IV

I was looking over my clock settings in processor expert and noticed that under Clock Source Setting 0 I can't select oscillator 1 as my MCG external referece clock source as seen below.  I currently have it set to RTC because there is nothing connected to oscillator 0, i.e., I don't have a crystal or reference clock connected to it.

Untitled7.png

According to the datasheet, there is clearly a third option which is System Oscillator 1 as seen below.

Untitled8.png

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Jorge_Gonzalez
NXP Employee
NXP Employee

Hello Daniel:

I honestly cannot help you with your USB problem, but I can help with your last question about clocks. You have 3 oscillators but only 2 of them (OSC0 and RTC) are selectable as external reference. The OSC1 can be used as reference for the PLL0 and PLL1. If you look in the PLL section, you will find OSC1 as an option. Check the next image:

K60_clocks.png

Hope this clarifies your doubt about clocks.

Regards!

Jorge Gonzalez

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danieldelatorre
Contributor IV

Jorge,

I re-read your comment about the clocks and thought of another point to make.  In your diagram you showed that the MCG mode is FEI which means that you will be using FLL rather than PLL which explains your point that the third MUX only has 2 options.  This is because FLL can only be used on the 32 kHz internal clock or OSC0.  In my particular case I'm using only PEE as my MCG mode which means that I'm using PLL and not FLL.  According to PE documentation the PEE's MCG output comes from PLL (i.e., PLL0 or PLL1) and PLL gets controlled by an external reference clock, below is a snippet from PE's help that pretty much says the same thing.  From the clock diagram it appears that the MCG external reference clock options for the PLL MUXs should be either OSC1 or OSC0 and not OSC0 or RTC right?

BTW, thanks for the help.  At the moment I need all the help I can get.

Untitled9.png

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Jorge_Gonzalez
NXP Employee
NXP Employee

Hello Daniel:

My answer applies disregarding of MCG mode, I was just talking about the internal MCU clock structure.

I think I can see you confusion here. You are confused by the repeated use of the words "External reference" for actually different things. This is a weakness in our documentation and in processor expert settings as well. In the next picture I try to show you my point:

1) In blue lines, are the "External references" for PLL0 and PLL1. These lines accept OSC0 and OSC1.

2) In red line, the "External reference" BUT for the whole MCG module. This clock is used as MCGOUTCLK in PBE, FBE and BLPE modes. This only allows selecting OSC0 and RTC.

I hope this is more clear.

Different_Ext_References.png

As for the USB problem, I think you can get help on MQX or Kinetis forum spaces. Try reposting in one of them:

Kinetis Microcontrollers

MQX Software Solutions

Regards!

Jorge Gonzalez

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danieldelatorre
Contributor IV

Thanks for clarifying, I'm using it this way so your comment is helpful in giving me confidence that my clock settings are correct.  Thank Jorge.

Hopefully somebody else can help me with my original problem.

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danieldelatorre
Contributor IV

I originally posted it in Kinetis Microcontrollers although Karla Denisse Mendoza Almanzar decided to move my post here.  I will re-post it, hopefully she doesn't move it again.

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