The ERCLK32K clock source does not appear to increment the LPTMR0 counter register on a KL26 (MKL26Z256VMC4 0N40H)

[nurichard]

Hello,

I am attempting to use the ERCLK32K clock source with the LPTMR0.  What I am finding is that the counter register (LPTMR0_CNR at 0x4004000c according to the KL26P121M48SF4RM v3.2 reference manual) is always read as zero.

I have configured the RTC to use the external oscillator for the 32,768kHz source and I can see the RT second and sub-second registers increases in agreement with a wall clock (RTC_TPR at 0x4003D000, RTC_TPR at 0x4003D004) so according to figure 5-1 in the RM, the ERCLK32K clock is working ok.

According to figure 5-4 in the RM, the only other clock selection bits are the LPTMRx_PSR[PCS] bits which should be set to 0b10 in the table within section 3.8.3.3 of the RM

I configure and start the LPTMR0 registers as follows:

"""

    // Ensure timer disabled

    LPTMR0_CSR &= ~LPTMR_CSR_TEN_MASK;

    // Timer interrupt enabled, timer reset when TCF raised, using timer mode, remaining disabled

    LPTMR0_CSR = LPTMR_CSR_TIE_MASK;

    // Ensure the compare register is set to 10s in units of 1024th of a second

    LPTMR0_CMR = 10240;

    // Select the ERCLK32K as the low power timer source, configure a prescaler of 32; counts in 1024th of a second

    LPTMR0_PSR = LPTMR_PSR_PRESCALE(0b0100) | LPTMR_PSR_PCS(0b10);

    // Start the timer

    LPTMR0_CSR |= LPTMR_CSR_TEN_MASK;

"""

At any time during those 10s, the LPTMR0_CNR always reads as zero rather than counting up as I believe it should.

At the end of time, the previously registered interrupt service routine executes after the correct interval so the timer is timing.

I cannot see anything in the latest errata that mentions any known mask problems (KINETIS_L_0N40H 09 AUG 2013).

Please could anyone kindly suggest what I am doing wrong,

My sincere thanks for your help,

Richard

[nurichard]

This same thing also appears to happen on MK10DN512V10 4N22D processors as well

[egoodii · Accepted solution]

This note is being added 'as available' to all Kinetis documents in the LPTMR section:

The CNR cannot be initialized, but can be read at any time. On each read of the CNR,

software must first write to the CNR with any value. This will synchronize and register

the current value of the CNR into a temporary register. The contents of the temporary

register are returned on each read of the CNR.

I don't know why that 'little secret' is so hard to find.

But it is in paragraph 33.4.5 of the aforementioned reference manual (It's new enough).

[nurichard]

Thank you,

The 'can't read' errors are definitely the most ironic and time consuming.

Thank you for your help,

Richard