TWRK65 unable to communicate to PHY (KSZ8041) while using TWR_SER board

[ameerhamza]

Dear all,

I am using custom bare-metal application and trying to establish communication between PHY [(KSZ8041) attached to TWR_SER board] and twr-k65f180m board, however if I attach twr-k70 board PHY works just fine but in case of twr-K65 PHY response is not read correctly. The problem is such that i can not read PHY_ID or read any PHY registers correctly, it always return with 0xffffff no matter whatever register i tried to read. I had configure MAC to operate in RMII mode and double checked the pin configuration. However i had a little doubt over RMII clocking, while reading K65 user manual, In last paragraph of section 3.1 it says we must provide 50 MHz clock to ENET_1588_CLKIN through TWR_SER Module. So i configured TWR_SER module to provide 50 MHz by selecting J2 (Jumper on TWR_SER module) to be set as 3-4 and J3 (Jumper on TWR_SER module) to be set as 2-3 and in TWR_K65 board i configured PTE26 as MUX ENET_1588_CLKIN and RMIISRC (bit 19 of register SIM_OPt2) as External bypass clock (ENET_1588_CLKIN). I have been stucked in this problem for a week now, If some one can tell me from current scenario what I am doing wrong, would be really helpful. Thanks in advance.

Kind Regards,

Hamza.

[mjbcswitzerland]

Hi Hamza

To use the TWR-K65F180M and the TWR-SER board for Ethernet operation you need to consider the following:
- MDIO is on PTB0 and MCD is on PTB1
- It is advisable to use a slow MDIO clock speed since there are only weak pull-ups and the capacitance of the tower back plane can cause poor signal integrity (slow rise times on open-drain outputs). Enable a pull-up on MDIO when the pins are configred since there are in fact no pull-ups in the HW.
- The ENET_1588_CLKIN pin should be configured correctly to accept the external 50MHz clock
- Also, this should be selected as source (rather than EXTAL) in SIM_SOPT2

Apart from that there is no further difference to the K70.
You can get a working reference from the links below that adapts itself to the processor in hand.

Regards

Mark

Kinetis: http://www.utasker.com/kinetis.html
Kinetis K65/K66:
- http://www.utasker.com/kinetis/TWR-K65F180M.html
- http://www.utasker.com/kinetis/FRDM-K66F.html
- http://www.utasker.com/kinetis/TEENSY_3.6.html
Networking: http://www.utasker.com/docs/uTasker/uTaskerNetworking.pdf

Free Open Source solution: https://github.com/uTasker/uTasker-Kinetis
Working project in 15 minutes video: https://youtu.be/K8ScSgpgQ6M

Professional Kinetis support, one-on-one training and complete fast-track project solutions: http://www.utasker.com/support.html

[ameerhamza · Accepted solution]

Hi Mark,

Thanks a lot for list of suggestions. After increasing PHY divider from 0x9 to 0xA, PHY is working fine, but i still have a little confusion. In TRM its written that for 50 MHZ, PHY divider should be set to 0x9, but PHY is only responsive if we keep this divider value less than or equal to 10. However its working fine for me now, but just asking out of curiosity.

Thanks,

Hamza