SPI DMA K66

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SPI DMA K66

785 Views
mdrasool_yadwad
Contributor II

Hello 

  I having configured SPI2 for communication with external EEPROM(SPI supported) using DMA.

I am not able to write the data on the external EEPROM correctly.

I am writing data using DMA channel 0 and reading using DMA channel 1. 

I don't know what's the problem and I am stuck in to it. 

below is my code please correct me if I am wrong

 

//SPI2 configuration

//-->Disable SPI
Spix->MCR |=0x01;
Spix->MCR &= (~SPI_MCR_MDIS_MASK);

//-->SPI in Master mode
Spix->MCR |= SPI_MCR_MSTR_MASK;

Spix->MCR |= SPI_MCR_ROOE_MASK;

//-->Enabling continuous clock
// Spix->MCR &=~SPI_MCR_CONT_SCKE_MASK;

//--> Disable Rx FIFO
Spix->MCR|=SPI_MCR_DIS_RXF_MASK;

//--> Disable Tx FIFO
Spix->MCR|=SPI_MCR_DIS_TXF_MASK;

//-->Clear RX and TX FIFO counters
Spix->MCR|=SPI_MCR_CLR_RXF_MASK;
Spix->MCR|=SPI_MCR_CLR_TXF_MASK;

//-->Peripheral Chip Select is Inactive Low
Spix->MCR |=SPI_MCR_PCSIS(1<<0);

//-->Frame Size
Spix->CTAR[0]= SPI_CTAR_FMSZ(0x07);

// BAUDRATE_625KHZ:
Spix->CTAR[0] |= SPI_CTAR_PBR(0x01);
Spix->CTAR[0] |= SPI_CTAR_BR(0x05);
Spix->CTAR[0] |= SPI_CTAR_DBR(0);

//SpiSetClockPhase
Spix->CTAR[0] |= SPI_CTAR_CPHA(0x00);

//SpiSetClockPolarity
Spix->CTAR[0] |= SPI_CTAR_CPOL(0x00);

//MSB First
Spix->CTAR[0] |= SPI_CTAR_LSBFE(0x00);

//SpiSetDelayAfterTX
Spix->CTAR[0] |= SPI_CTAR_DT(0x01);

//SetDelayAfterSCK
Spix->CTAR[0] |= SPI_CTAR_ASC(0x01);

//SetDelayAfterPCS
Spix->CTAR[0] |= SPI_CTAR_CSSCK(0x01);

//SpiSetDelayAfterPCSSCK
Spix->CTAR[0] |= SPI_CTAR_PCSSCK(0x00);

//SpiSetDelayAfterPDT
Spix->CTAR[0] |= SPI_CTAR_PASC(0x00);

          //SpiSetDelayAfterPDT
         Spix->CTAR[0] |= SPI_CTAR_PDT(0x00);

      //For DMA request
        Spix->RSER |=         (SPI_RSER_TFFF_RE_MASK|SPI_RSER_TFFF_DIRS_MASK|SPI_RSER_RFDF_RE_MASK|SPI_RS         ER_RFDF_DIRS_MASK);

//SPI config completes here

//DMAMUX configuration
       //Enable clock for DMA multiplexer
      SIM->SCGC6 |= SIM_SCGC6_DMAMUX_MASK;
     //Enable clock for DMA
     SIM->SCGC7 |= SIM_SCGC7_DMA_MASK;
      DMAMUX->CHCFG[0] |= DMAMUX_CHCFG_ENBL_MASK | DMAMUX_CHCFG_SOURCE(39);
      DMAMUX->CHCFG[1] |= DMAMUX_CHCFG_ENBL_MASK | DMAMUX_CHCFG_SOURCE(38);

 

//DMA Transmit config

        //source address
         DMA0->TCD[0].SADDR = (uint32_t)spi_buff;

          /* Source offset disabled */
          DMA0->TCD[0].SOFF = 0x00;
          DMA0->TCD[0].DOFF = 0x00;

          DMA0->TCD[0].SLAST = 0x00;

         //Source data transfer size and Destination data transfer size
          DMA0->TCD[0].ATTR = DMA_ATTR_SSIZE(0x00)|DMA_ATTR_DSIZE(0x00);

           DMA0->TCD[0].NBYTES_MLNO= 0x01;

          //stop the DMA activity once the single buffer transfer completes
           DMA0->TCD[0].CSR |= DMA_CSR_DREQ_MASK;

          //Destination address
           // SPI0->0x4002C034, SPI1->0x4002D034, SPI2->0x400AC034 Push register address
           DMA0->TCD[0].DADDR =0x400AC034;

            /* No adjustment to destination address */
            DMA0->TCD[0].DLAST_SGA = 0x00;

         //Current Major Iteration Count
          DMA0->TCD[0].CITER_ELINKNO = DMA_CITER_ELINKNO_CITER(1);

          //Starting Major Iteration Count
          DMA0->TCD[0].BITER_ELINKNO = DMA_BITER_ELINKNO_BITER(1);

         //Set enable request
         DMA0->SERQ |= DMA_SERQ_SERQ_MASK;

           //Channel Start
            DMA0->TCD[0].CSR = DMA_CSR_START_MASK;

//DMA transmit ends here

 

 

//DMA Receive Starts

       //source address
      //SPI0->0x4002C038, SPI1->0x4002D038, SPI2->0x400AC038 POP register
       DMA0->TCD[1].SADDR = 0x400AC038;

       /* Source offset disabled */
        DMA0->TCD[1].SOFF = 0x00;
         DMA0->TCD[1].DOFF = 0x00;

       DMA0->TCD[1].SLAST = 0x00;
 
          //Source data transfer size and Destination data transfer size
      DMA0->TCD[1].ATTR = DMA_ATTR_SSIZE(0x00)|DMA_ATTR_DSIZE(0x00);

      DMA0->TCD[1].NBYTES_MLNO= 0x01;

     //stop the DMA activity once the single buffer transfer completes
     DMA0->TCD[1].CSR |= DMA_CSR_DREQ_MASK;

     //Destination address
     // SPI0->0x4002C034, SPI1->0x4002D034, SPI2->0x400AC034 Push register address
     DMA0->TCD[1].DADDR =(uint32_t)spi_buff;

    /* No adjustment to destination address */
    DMA0->TCD[1].DLAST_SGA = 0x00;

       //Current Major Iteration Count
       DMA0->TCD[1].CITER_ELINKNO = DMA_CITER_ELINKNO_CITER(1);

       //Starting Major Iteration Count
      DMA0->TCD[1].BITER_ELINKNO = DMA_BITER_ELINKNO_BITER(1);

      //Set enable request
      DMA0->SERQ |= DMA_SERQ_SERQ_MASK;

     //Channel Start
     DMA0->TCD[1].CSR = DMA_CSR_START_MASK;

//DMA receive ends here

 

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766 Views
Omar_Anguiano
NXP TechSupport
NXP TechSupport

Hello mdrasool_yadwad

 

I suggest you to use these documents as a reference to make the SPI and DMA work: https://community.nxp.com/t5/Kinetis-Microcontrollers/Using-the-DMA-module-in-Kinetis-Devices/ta-p/1.... Also I suggest you use the SDK examples of DSPI with DMA.

 

Let me know if this is helpful, if you have more questions do not hesitate to ask me.

Best regards,

Omar

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mdrasool_yadwad
Contributor II

The problem I am facing is after triggering the DMA the data is loading into push register but after completion of transfer the TCF bit is setted which is not cleared automatically when i use DMA

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Omar_Anguiano
NXP TechSupport
NXP TechSupport

Hello

 

The TCF field is cleared writing a 1 to it. Once it is set it is not cleared until 1 is written to it.

 

Let me know if this is helpful, if you have more questions do not hesitate to ask me.

Best regards,

Omar

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mdrasool_yadwad
Contributor II

then what is the use of using DMA. For every byte we send using DMA we have to clear the TCF. but when we send 10 bytes using DMA how to clear the TCF.

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