Hi ZhongYao,
The RESET_b pin, if enabled, must have a 100 nF capacitor close to the MCU for transient protection. The NMI_b pin, if enabled, must not have any capacitance connected to it. Each pin, when enabled as their default function, has a weak internal pullup, but an external 4.7 kΩ to 10 kΩ pullup is recommended.
After reset, the shared peripheral functions are disabled so that the pins are controlled by the parallel I/O except PTA4, PTA0, PTB4 and PTA5 that are default to SWD_DIO, SWD_CLK, NMI and RESET function. Driving the NMI signal low forces a non-maskable interrupt, if the NMI function is selected on the corresponding pin.
If you hope the PTB4(deault as NMI_b function) as SPI0_MISO, please modify the NMIE bit in SIM_SOPT register first.

I think you can configure PTB1 as SPI0_MISO function instead of using PTB4(NMI_b).
Then configure PTA3 as UART0_TX and PTA2 as UART0_RX. (Please note that PTA2 and PTA3 are true open-drain pins when operated as output.)
If you want use the debugger on FRDM-KEAZ128, please isolate the on-board MCU from the debug interface. (for example don't use the R101)
Best Regards,
Robin
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