S9KEAZN8AMFK Exposed Pad Connection Problems

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S9KEAZN8AMFK Exposed Pad Connection Problems

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54anson
Contributor I

Hi,

   I am use FRDM-KEAZ128Q80 as OpenOCD debugger, and it works well on a S9KEAZ128AMLH chip. but when I try to debug a S9KEAZN8AMFK mcu ,It doesn't work. It can't reconize the mcu.

  I have connected the Exposed Pad to the ground, I searched the <KEA8 Sub-Family Reference Manual> but I don't found how to deal with the Exposed Pad.

My schematic has been attached. *Note that I have been conncted the Exposed Pad to the ground.

I tested the pin PTA5/RESET voltage is 2.8v , it is very strange. help me please .

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1 Solution
989 Views
Robin_Shen
NXP TechSupport
NXP TechSupport

Hi ZhongYao,

The RESET_b pin, if enabled, must have a 100 nF capacitor close to the MCU for transient protection. The NMI_b pin, if enabled, must not have any capacitance connected to it. Each pin, when enabled as their default function, has a weak internal pullup, but an external 4.7 kΩ to 10 kΩ pullup is recommended.

After reset, the shared peripheral functions are disabled so that the pins are controlled by the parallel I/O except PTA4, PTA0, PTB4 and PTA5 that are default to SWD_DIO, SWD_CLK, NMI and RESET function. Driving the NMI signal low forces a non-maskable interrupt, if the NMI function is selected on the corresponding pin.

If you hope the PTB4(deault as NMI_b function) as SPI0_MISO, please modify the NMIE bit in SIM_SOPT register first.

NMIE.png

I think you can configure PTB1 as SPI0_MISO function instead of using PTB4(NMI_b).

Then configure PTA3 as UART0_TX and PTA2 as UART0_RX. (Please note that PTA2 and PTA3 are true open-drain pins when operated as output.)

If you want use the debugger on FRDM-KEAZ128, please isolate the on-board MCU from the debug interface. (for example don't use the R101)

Best Regards,

Robin

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3 Replies
989 Views
54anson
Contributor I

Thanks to Robin, problems has been solved. These problems cased by NMI_b pin connection, I cut the NMI_b wire on my pcb then it could be recognized by J-Link.   Thank you!

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990 Views
Robin_Shen
NXP TechSupport
NXP TechSupport

Hi ZhongYao,

The RESET_b pin, if enabled, must have a 100 nF capacitor close to the MCU for transient protection. The NMI_b pin, if enabled, must not have any capacitance connected to it. Each pin, when enabled as their default function, has a weak internal pullup, but an external 4.7 kΩ to 10 kΩ pullup is recommended.

After reset, the shared peripheral functions are disabled so that the pins are controlled by the parallel I/O except PTA4, PTA0, PTB4 and PTA5 that are default to SWD_DIO, SWD_CLK, NMI and RESET function. Driving the NMI signal low forces a non-maskable interrupt, if the NMI function is selected on the corresponding pin.

If you hope the PTB4(deault as NMI_b function) as SPI0_MISO, please modify the NMIE bit in SIM_SOPT register first.

NMIE.png

I think you can configure PTB1 as SPI0_MISO function instead of using PTB4(NMI_b).

Then configure PTA3 as UART0_TX and PTA2 as UART0_RX. (Please note that PTA2 and PTA3 are true open-drain pins when operated as output.)

If you want use the debugger on FRDM-KEAZ128, please isolate the on-board MCU from the debug interface. (for example don't use the R101)

Best Regards,

Robin

-----------------------------------------------------------------------------------------------------------------------

Note: If this post answers your question, please click the Correct Answer button. Thank you!

-----------------------------------------------------------------------------------------------------------------------

633 Views
Romeo
Contributor I

Hi Robin

I made an automotive product using S9KEAZN8AMFK.
I know that S9KEAZN8AMFK is AEC-Q100 Grade 1.
And the company we supply products to says they need an AEC-Q100 Grade 1 certification test report.
I must submit proof that S9KEAZN8AMFK is AEC-Q100 Grade 1.

Can you send me the AEC-Q100 Grade 1 certification test report?

Best Regards,

romeo

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