Hi Max Vilimpoc
Sorry for the late reply, About your questions:
1. Does NXP plan to have a specific location in flash where production trim data (as measured by NXP at the factory) will be written?
No, This locations is defined with that address because is the last flash sector, but as you may guess, different devices has different flash sizes, so this address can not be standardized. actually this sector is just defined for the wireless stack, in this area is reserved and contains hardware-specific parameters and most of them are for wireless stack:
typedef PACKED_STRUCT hardwareParameters_tag
{
uint8_t identificationWord[10];
uint8_t reserved[32];
uint8_t ieee_802_15_4_address[8];
uint8_t bluetooth_address[6];
uint32_t xtalTrim;
uint32_t edCalibrationOffset;
uint32_t pllFStepOffset;
uint32_t gInternalStorageAddr;
uint16_t hardwareParamsCrc;
}hardwareParameters_t;
2. Could NXP provide reference documentation on the trim data structures it uses for its various microcontroller families?
As I mentioned this area is reserved just in the wireless stack, for the Kinetis W family, in other kinetis family you may not find a reserved area like this. You can consult the Connectivity Framework Reference Manual, chapter 3.5.6 "Production Data Storage" for you reference, you can locate it in the path: <MKW41Z_ConnSw_1.0.2_installed_path>\docs\wireless\Common
3. Could NXP specify a trim area in flash at a much lower address? i.e. for many Kinetis microcontrollers, location 0x410 is already used for the Flash Configuration Field (FCF), so it might be a convenient convention to store trim data from 0x480 - 0x500.
Actually it is just a reserved area for information storage, it doesn't set or configure anything, it has not information until you write it, and as I mentioned, this address was selected because it is the last flash sector, this sector is not erased/written at code download time.
Hope this information helps you
Have a great day,
Jorge Alcala
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