PDB Interrupt

[pmt]

I'm looking to use the PDB for one-shot interrupt generation (I'm not driving DACs or ADC, just looking for interrupt generation).  While I can get the Interrupt Flag (PDBIF) to go active I can't get my interrupt to actually vector.  I noticed in the PDB block diagram that the interrupt appears to be gated by TOEx.  But this is somewhat confusing, as I don't want to involve the DAC triggers at all.  Can anyone provide help?  What is the mystery setting to get interrupt to fire?

My setup code:

// Enable PDB clock

SIM->SCGC6 |= SIM_SCGC6_PDB_MASK;

// Set timeout

PDB0->IDLY = PDB_IDLY_IDLY(0x7fff);

PDB0->SC = 

  PDB_SC_SWTRIG_MASK | // Software trigger

  PDB_SC_TRGSEL(0xF) | // Software trigger select

  PDB_SC_PDBEN_MASK  | // Enable PDB

  PDB_SC_PDBIE_MASK  | // Enable Interrupt

  PDB_SC_LDOK_MASK; // Load OK

[ndavies]

Did you enable the NVIC to pass the interrupt through to the processor?

[pmt]

I didn’t explicitly enable anything in the NVIC, but I think my environment already has this set up. I’m not having any issues with any other interrupts such as UART, SPI, FTM, etc. A quick scan in my debugger shows every NVIC register value at 0.

[ndavies · Accepted solution]

All zeros is the NVICs reset state. All Zeros will stop all interrupts above Int 15 from being passed through. Interrupts 0-15 are not connected through the NVIC.

You should see one bit set for each active interrupt in the NVIC_ISER0 - NVIC_ISER31 registers.

The PDB's interrupt must be enabled through one of the NVIC_ISERx registers. If I did my math correctly, it would be NVIC_SER2 bit 8. ( Register = ((Int 88-16) /32), Bit = ((Int 88-16)%32) ) That bit needs to be set for the PDB interrupt to get through to the core. The PDB interrupt will not work without the NVIC bit being set.

I enable the NVIC bit at the same time I enable the interrupt. Your environment may be doing this for the other interrupts. Check to make sure this is happening.

[pmt]

Just a follow up. There seems to be a race condition with this interrupt. Using this ISR code:

// Instrumentation

static volatile uint_32 PdbCounter = 0;

void PDB0_IRQHandler(void)

{

PdbCounter++;

PDB0->SC &= (~PDB_SC_PDBIF_MASK);

// Insert NOP to avoid ISR exit race condition

__asm("nop");

return;

}

On every software trigger my PcbCounter increments by 2 when the __asm(“nop”); is removed, but increments by 1 with the nop included. Seems like the interrupt flag condition does not clear fast enough. Perhaps because the peripheral clock is slower than the core clock?

[frankvanhooft]

I've seen this on other ARM processors as well - what you're seeing is not unique to Kinetis. It's because the interrupt clear hasn't had time to propagate through the NVIC before you exit the ISR, resulting in you immediately re-entering your ISR. One solution is what you suggest, putting a nop at the end of your code, to give a little more time after the clear. Another possibility (and is what I do) is to clear the interrupt at the very start of your ISR. In your ISR example, swap the first two lines of code.

Frank.

[pmt]

Yea, sigh…. That was it:

NVIC_EnableIRQ(PDB0_IRQn);

Interrupt is working now.

Thanks!