If I hold the Kinetis MK64FN1M0VMD12 in reset, will the processor go in tri-state mode/high impedance? I couldn't find this in the datasheet (I might have missed it)
Thanks in advance!
Hi,
During the reset, besides of JTAG pins, EzPort pins, power pins and external oscillator pins are enabled, other pins are high-impedance(disable).
Hope this information can help you
Best Regards,
Adrian Sanchez Cano
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From K64P144M120SF5RM.pdf:
55.2.6, the definition for Port Data Direction Registers (GPIOx_PDDR) shows all reset to 'all zero', so that defines all GPIO-mode-pins as 'input' (high impedance).
The next question is 'which pins are GPIO at reset', and for that we jump over to table 10-2, and more particularly 10.3.1 'default' column, to see that 'most port pins' default to the analog-input modes, crystal, or disabled (ALT0). So, NOT GPIO, but high-impedance nonetheless.
Are you expecting more information?