KV58 SPI communication

[a8Chcx]

Hi,

I am using KV58 SPI to read and write SPI SRAM(IS62WVS2568).

I am following the sample code "dspi_polling_b2b_transfer_master" to poll the mode register, but I can't get 0x40(default) when I send the command = 0x05.

I am using PCS1 for SRAM, PCS0 for SPI flash. Both are not working...

1) When I choose PCS1 with low active, and I can see PCS0 is LOW. Do I need to configure PCS0 to HIGH? How about other PCS2~~5 on SPI0? For now, I configure PCS2~~5 as input GPIO. Do I need to configure them as well?

2) When I read, I always get 0x00 as return.

Thanks,

Christie

[diego_charles · Accepted solution]

I have tried to replicate the problem using the example  dspi_interrupt from SDK. It uses only the TWR-KV58. In the example, the SPI0 is set for master and SPI1 for slave. After a successful transmission is put on console: DSPI transfer all data matched! 

 My goal was to enable the PCS1 and PCS0 in the SPI0 and alternate their usage for select master. Note that the other ones where ignored.

/* PORTE16 (pin 18) is configured as SPI0_PCS0        enable PCS1 alternative ********************** */

PORT_SetPinMux(PORTE, 16U, kPORT_MuxAlt2);

/* PORTC3 (pin 3) is configured as SPI0_PCS1            enable PCS1 alternative     ******************/

PORT_SetPinMux(PORTC, 3U, kPORT_MuxAlt2);

….

    masterConfig.whichPcs           =  kDSPI_Pcs0  ;  /* use two PCS pins with  slave select as active low */

    masterConfig.whichPcs          |=  kDSPI_Pcs1  ; 

  masterConfig.pcsActiveHighOrLow = kDSPI_PcsActiveLow;

…

  DSPI_MasterInit(EXAMPLE_DSPI_MASTER_BASEADDR, &masterConfig, srcClock_Hz);

After the call of DSPI_MasterInit , the logic level on PCS1 and PCS0 is true.

Now, for select the which PCS pin to use, it is only necessary to  assign it, as the following sentences

/* Start master transfer*/

commandData.whichPcs           = kDSPI_Pcs1 ; // or kDSPI_Pcs0

…

 masterCommand = DSPI_MasterGetFormattedCommand(&commandData);

After the PCS pins had been selected for a new transfer the transfer will begin with this function.

/* Start DSPI transfer.*/

    DSPI_StartTransfer(EXAMPLE_DSPI_MASTER_BASEADDR);

I had made successfully two transfers, one with PCS1 and another with PCS0.  The PCS pins behave in the correct way in this example. I had attached their oscilloscope captures. In both captures, the PCS0 is on a yellow color and PCS1 pink.  There the signal values were at zero level after reset, in one after  DSPI_MasterInit  , and finally during transfer, only one toggle his state.

I recommend you to try this example as well because that must be the normal behavior of PCS pins.

Please let me know your results, and if this was helpful.

Have a great day,
Diego

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[diego_charles]

Hello, Christie

Sorry for any inconveniences, could you provide, in code example, the steps you are following to configure the PCSx pins for the  dspi driver. We will try to replicate the problem.
Have a great day,
Diego

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[a8Chcx]

Hi Diego,

Here is from my pin_mux for SPI0:

If I am using the following sample code, I can't receive the data properly. But if I change the PCS0 and PCS1 as GPIO, Set to LOW before transfer and Set to HIGH after transfer, everythinh is working fine.

1) I tried on several devices, SPI flash, SPI SRAM, and FXOS8700, they are the same result...

2) I checked PCS0 and PCS1, LOW and HIGH changes look fine as well even if I use PCS0 or PCS1...

Regards,

Christie

......

//-----*****Configure SPI0 for SPI devices*****-----

 PORT_SetPinMux(PORTC, PIN3_IDX, kPORT_MuxAlt2); /* V5.1(IS62_CS) & V5.0(RX1)---PORTC3 (pin 106) is configured as SPI0_PCS1 */

//PORT_SetPinMux(PORTC, PIN3_IDX, kPORT_MuxAsGpio); /* V5.1(IS62_CS) & V5.0(RX1)---PORTC3 (pin 106) is configured as SPI0_PCS1 */

 PORT_SetPinMux(PORTC, PIN4_IDX, kPORT_MuxAlt2); /* V5.1(IS25_CS) & V5.0(TX1)---PORTC4 (pin 109) is configured as SPI0_PCS0 */

//PORT_SetPinMux(PORTC, PIN4_IDX, kPORT_MuxAsGpio); /* V5.1(IS25_CS) & V5.0(TX1)---PORTC4 (pin 109) is configured as SPI0_PCS0 */

PORT_SetPinMux(PORTC, PIN5_IDX, kPORT_MuxAlt2); /* V5.1(DCLK) & V5.0(INX2)---PORTC5 (pin 110) is configured as SPI0_SCK */

PORT_SetPinMux(PORTC, PIN6_IDX, kPORT_MuxAlt2); /* V5.1(DATA_OUT) & V5.0(INX3)---PORTC6 (pin 111) is configured as SPI0_SOUT */

PORT_SetPinMux(PORTC, PIN7_IDX, kPORT_MuxAlt2); /* V5.1(DATA_IN) & V5.0(INX4)---PORTC7 (pin 112) is configured as SPI0_SIN */

.....

Here is the code from sample code:

// Master config

masterConfig.whichCtar = kDSPI_Ctar0;

masterConfig.ctarConfig.baudRate = FLASH_RAM_TRANSFER_BAUDRATE;

masterConfig.ctarConfig.bitsPerFrame = 8U;

masterConfig.ctarConfig.cpol = kDSPI_ClockPolarityActiveHigh;

masterConfig.ctarConfig.cpha = kDSPI_ClockPhaseFirstEdge;

masterConfig.ctarConfig.direction = kDSPI_MsbFirst;

masterConfig.ctarConfig.pcsToSckDelayInNanoSec = 1000000000U / FLASH_RAM_TRANSFER_BAUDRATE;

masterConfig.ctarConfig.lastSckToPcsDelayInNanoSec = 1000000000U / FLASH_RAM_TRANSFER_BAUDRATE;

masterConfig.ctarConfig.betweenTransferDelayInNanoSec = 1000000000U / FLASH_RAM_TRANSFER_BAUDRATE;

// masterConfig.whichPcs = kDSPI_Pcs0; // FOX8700//EXAMPLE_DSPI_MASTER_PCS_FOR_INIT;

// masterConfig.whichPcs = kDSPI_Pcs1; // IS62/65 SRAM---PCS1//EXAMPLE_DSPI_MASTER_PCS_FOR_INIT;

masterConfig.whichPcs = kDSPI_Pcs0; // IS25W Flash---PCS0//EXAMPLE_DSPI_MASTER_PCS_FOR_INIT;

masterConfig.whichPcs = FLASH_DSPI0_MASTER_PCS_FOR_INIT;

masterConfig.whichPcs |= 0x3F; // I have to add this to keep other PCS1 HIGH???

masterConfig.pcsActiveHighOrLow = kDSPI_PcsActiveLow; // ==1

masterConfig.enableContinuousSCK = false;

masterConfig.enableRxFifoOverWrite = false;

masterConfig.enableModifiedTimingFormat = false;

masterConfig.samplePoint = kDSPI_SckToSin0Clock;　

srcClock_Hz = unint32_temp0 = FLASH_RAM_DSPI0_MASTER_CLK_FREQ;;

//PRINTF("\r\n\r\nDSPI board to board polling example=%d_%d_%d_%d\r\n", FLASH_RAM_DSPI0_MASTER_CLK_FREQ, unint32_temp0, FLASH_RAM_TRANSFER_BAUDRATE, (1000000000U / FLASH_RAM_TRANSFER_BAUDRATE));

DSPI_MasterInit(EXAMPLE_DSPI_MASTER_BASEADDR, &masterConfig, srcClock_Hz);

　

masterTxData[0] = 0x05; // Read Mode Register

masterTxData[1] = DSPI_DUMMY_DATA; //0x00; // Read Mode Register

masterTxData[2] = DSPI_DUMMY_DATA; //0x00; // Read Mode Register

masterTxData[3] = DSPI_DUMMY_DATA; //0x00; // Read Mode Register

 masterRxData[0] = 0xa5;

 masterRxData[1] = 0xa5;

 masterRxData[2] = 0xa5;

 masterRxData[3] = 0xa5;

// // Print out transmit buffer

PRINTF("\r\nFLASH_TX0:%02X_%02X_%02X_%02X_%02X", masterTxData[0], masterTxData[1], masterTxData[2], masterTxData[3], masterRxData[0]);

// // Start master transfer, send data to slave

masterXfer.txData = masterTxData;

masterXfer.rxData = NULL;

masterXfer.dataSize = 1; // TRANSFER_SIZE;

masterXfer.configFlags = kDSPI_MasterCtar0 | EXAMPLE_DSPI_MASTER_PCS_FOR_TRANSFER | kDSPI_MasterPcsContinuous;

// Start SPI operation

DSPI_MasterTransferBlocking(EXAMPLE_DSPI_MASTER_BASEADDR, &masterXfer);

// Delay to wait slave is ready

for (i = 0U; i < EXAMPLE_DSPI_DEALY_COUNT; i++)

{

 __NOP();

 }

// Start master transfer, receive data from slave

masterXfer.txData = NULL;

masterXfer.rxData = masterRxData;

masterXfer.dataSize = 1; // TRANSFER_SIZE;

masterXfer.configFlags = kDSPI_MasterCtar0 | EXAMPLE_DSPI_MASTER_PCS_FOR_TRANSFER | kDSPI_MasterPcsContinuous;

DSPI_MasterTransferBlocking(EXAMPLE_DSPI_MASTER_BASEADDR, &masterXfer);

....

[a8Chcx]

Hi,

I am trying to configure PCSx signal as GPIO, and set to LOW during sending and receiving, set to HIGH after finishing.

Then I can get the right response.

Can anyone tell where I need to change the configuration if I still use PCSx?

Thanks,

Christie

[a8Chcx]

Hi,

I am trying to communicate with FXOS8700 over SPI and got the same result.

I have to control PCSx manually. Otherwise, I can't communicate with FXOS8700.

Can anyone tell me where the problem is and how to fix it?

Thanks,

Christie