KL28 clock distribution

[mst_]

Hello,

I've got some questions regarding KL28 clock distribution subsystem. Please, can someone clarify the following?

1.) FIRC clock source has auto-trim feature. How is SCG_FIRCTCFG_TRIMDIV supposed to be set when SOSC is used as trim reference?

2.) RTC_CR contains SCxP load capacitor configuration bits and OSCE for oscillator control. SCG contains similar fields (SCG_SOSCCFG_SCxP and SCG_SOSCCSR_SOSCEN). How are RTC and SCG oscillator settings related?

3.) SCG_SOSCCSR contains SOSCERCLKEN bit that is described as "System OSC 3V ERCLK Enable" in refman rev. 4. What does "3V" means? Is this the same clock tree as ERCLK?

Thank you.

Best regards,

Martin

[Hui_Ma]

Hi,

I got the answer about question 1, please check below comments.

1.) FIRC clock source has auto-trim feature. How is SCG_FIRCTCFG_TRIMDIV supposed to be set when SOSC is used as trim reference?

TS: The FIRC pre-divider is intended for the SOSC and the expectation is to set the div ratio to give  a 31250khz divided clock.

Wish it helps.

Have a great day,
Ma Hui

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[Hui_Ma]

Hi,

1> I am checking with Kinetis product team to get the question 1 answer. I will let you know later;

2> The SCG module provides the system crystal oscillator, the SCG_SOSCCFG_SCxP and SCG_SOSCCSR_SOSCEN registers bits used to control the system crystal oscillator.
The RTC module register doesn't have related 32KHz oscillator, the related capacitor load bit has no function. The RTC used OSC32KCLK is from SCG output from the SOSC.

More detailed info, please check KL28 reference manual chapter 5.8.1 OSC32KCLK.

3> It is the same clock source of SCG ERCLK (clock from EXTAL0 pin). The 3V means the KL28 system OSC is 3V chip, which doesn't support 5V clock input.

Have a great day,
Ma Hui

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