KL28 LPI2C arbitration lost error

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KL28 LPI2C arbitration lost error

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liangliangma
Contributor II

Hi,

I am using the LPI2C module in KL28 to read from a device whose power supply is turned off periodically. If the power losing occurred during transfer and SCL is high, the SDA will be released by the device and goes to high, and LPI2C module will recognize it as an STOP condition, it then sets the arbitration lost flag [ALF] and bus busy flag [BBF], and quit.

The ALF can be cleared by write a 1, but the BBF keeps set and cannot generate START condition anymore. Is there any way to restore the module without a soft reset?

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jorge_a_vazquez
NXP Employee
NXP Employee

Hi Liangliang Ma

According to the Reference Manual, BBF flag is set when LPI2C master is enabled and activity detected on I2C bus, but STOP condition has not been detected and bus idle timeout (if enabled) has not occurred.

So the way that you can clear BBf flag is if you disable LPI2C master and then you enable it again, so before you clear ALF, you could diable and enable the LPI2C module with the LPI2C_MCR[MEN] bit.

Another method is if you use the bus idle timeout, BUSIDLE, this configures the bus idle timeout period in clock cycles and If both SCL and SDA are high for longer than BUSIDLE cycles, then the I2C bus is assumed to be idle and the master can generate a START condition


Hope this information helps you
Have a great day,
Jorge Alcala

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jorge_a_vazquez
NXP Employee
NXP Employee

Hi Liangliang Ma

According to the Reference Manual, BBF flag is set when LPI2C master is enabled and activity detected on I2C bus, but STOP condition has not been detected and bus idle timeout (if enabled) has not occurred.

So the way that you can clear BBf flag is if you disable LPI2C master and then you enable it again, so before you clear ALF, you could diable and enable the LPI2C module with the LPI2C_MCR[MEN] bit.

Another method is if you use the bus idle timeout, BUSIDLE, this configures the bus idle timeout period in clock cycles and If both SCL and SDA are high for longer than BUSIDLE cycles, then the I2C bus is assumed to be idle and the master can generate a START condition


Hope this information helps you
Have a great day,
Jorge Alcala

-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

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