KL02 Input voltage operating requirements

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KL02 Input voltage operating requirements

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Contributor II

Please help to confirm the below questions,

  1. 1) The below waveform is our test waveform, and the test condition is:
  2. Ch1 is input signal to pin11, and Ch2 is output signal from pin22
  3. Pin11 and pin22 are configured GPIO
  4. The logic level of Ch2 is the same with Ch1. For example, if Ch1 goes high, then Ch2 goes high too.

未命名.png

DSC_0437.JPG

From the datasheet, the input high voltage of KL02 device is about 3.3V * 0.7 = 2.31V.

But, according to our experiment, the output signal goes high even the input signal is about 1.43V ~ 1.89V. Please help to check the input high/low voltage level.

The CH1 max voltage is 1.89V, min voltage is 1.43V, it's available without this voltage range.

03.png

Please help to confirm input high/low voltage level first, thanks.

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Senior Contributor II

Hello Kris,

I recreated the scenario and as you can see in the image shown below, I found very similar results

pastedImage_0.jpg

The rising edge will toggle the pin's input buffer at about 0.7 * VDD Volts while the falling edge will toggle the input buffer at about 0.35 * VDD Volts. These are the actual input buffer transition points, also known as threshold voltages. The VIL and VIH calculations are to guarantee logic levels – the switch points are well within the VIL/VIH specs. The input buffer thresholds change with VDD, temp, and process, so we cannot guarantee the switchpoint voltages, however, they are within the VIL/VIH limits. And, the difference between the switchpoints will be at least as much as the hysteresis spec, which is about 200mV at VDD = 3.3V.

Please let me know if this information is useful or if I can do anything else for you.

Best regards,

Earl Orlando.

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Senior Contributor II

Hello Kris,

I recreated the scenario and as you can see in the image shown below, I found very similar results

pastedImage_0.jpg

The rising edge will toggle the pin's input buffer at about 0.7 * VDD Volts while the falling edge will toggle the input buffer at about 0.35 * VDD Volts. These are the actual input buffer transition points, also known as threshold voltages. The VIL and VIH calculations are to guarantee logic levels – the switch points are well within the VIL/VIH specs. The input buffer thresholds change with VDD, temp, and process, so we cannot guarantee the switchpoint voltages, however, they are within the VIL/VIH limits. And, the difference between the switchpoints will be at least as much as the hysteresis spec, which is about 200mV at VDD = 3.3V.

Please let me know if this information is useful or if I can do anything else for you.

Best regards,

Earl Orlando.

/* If this post answers your question please click the Correct Answer button. */

View solution in original post

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Contributor II

Hi Earl

Thanks your feedback.

As I know, From theory, the I/O cell is an CMOS circuit, Does the a middle voltage will turn on both MOS gate which will leads to damage?

Is there any suggestions to address this issue?

What if we have an logic I/O to the KL02, but the slew rate of the signal is a bit slow, will there be an issue for the VIH/VIL?

If so, what is the acceptable slew rate for the I/O ports in your device.

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Senior Contributor II

Hello Kris,

I am sorry for the delay on my part. The middle voltage range does not damage the I/O cell. The only one issue that you could experiment is the change of the thresholds to toggle from low to high and vice-versa.

Best regards,

Earl.

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