KBI Interrupt on KE02

[lmg]

I am attempting to use the KBI0, Pin 1 Interrupt on a KE02Z processor.

I am using Kinetis Design Studio 3.2.0 with Processor Expert version shown below:

The KBI Processor Expert (Sync_Int:init_KBI) component looks like this:

and appears to be a bit incomplete.

I've modified/added-to the automatically-generated code and here's what I have so far:

/*
** ===================================================================
** Method : Sync_Int_Init (component Init_KBI)
** Description :
** This method initializes registers of the KBI module
** according to the Peripheral Initialization settings.
** Call this method in user code to initialize the module. By
** default, the method is called by PE automatically; see "Call
** Init method" property of the component for more details.
** Parameters : None
** Returns : Nothing
** ===================================================================
*/
void Sync_Int_Init(void)
{
// Connect system clock to KBI0 module (not well documented)
SIM_SCGC |= SIM_SCGC_KBI0_MASK;
/* KBI0_SC: ??=0,??=0,??=0,??=0,KBF=0,KBACK=0,KBIE=0,KBMOD=0 */
KBI0_SC = 0x00;
/* KBI0_ES: KBEDG=2 */
KBI0_ES = KBI_ES_KBEDG(0x02);
/* KBI0_PE: KBIPE=2 */
KBI0_PE = KBI_PE_KBIPE(0x02);
/* KBI0_SC: KBACK=1 */
KBI0_SC |= KBI_SC_KBACK_MASK;
/* KBI0_SC: KBIE=1 */
KBI0_SC |= KBI_SC_KBIE_MASK;
}

/*
** ###################################################################
**
** The interrupt service routine(s) must be implemented
** by user in one of the following user modules.
**
** If the "Generate ISR" option is enabled, Processor Expert generates
** ISR templates in the CPU event module.
**
** User modules:
** main.c
** Events.c
**
** ###################################################################
** */
PE_ISR(Sync_Interrupt)
{

/* KBI0_SC: KBIE=1 */
KBI0_SC |= KBI_SC_KBACK_MASK;

... <my code here>

}

I can download the code and KBI seems to initialize ok, but the ISR is never called.

I found this post:

Making a KBI Library... 

which (at the end of the reply) references NVIC_ICER and NVIC_IPER6. I see documentation on the second register - just a place to set the interrupt priority. But what is NVIC_ICER? I don't see that even mentioned in the reference manual. Is there a bit in that register that turns on the KBI interrupt?

Thanks in advance for any insight you can provide.

~LMG

[Robin_Shen · Accepted solution]

Here is the NVIC register summary, see NVIC_ISER and NVIC_ICER:

The Interrupt vector assignments of KBI0 in KE02 are same as KE04, you can use the codes in that post.

From your codes, rising edge is configured for this pin. Did you enable internal pull-down or put external pull-down for KBI0 pin1?

Here the "deasserted logic levels" is 0v for your configuration.

Best Regards,

Robin

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[lmg]

Thanks! Very helpful summary.

~LMG

[mjbcswitzerland]

Hi

See the ARM core documentation, which is not included in the user's manual: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0662b/Cihbiadi.html

Regards

Mark

[uTasker project developer for Kinetis and i.MX RT]