K82 : cache and cache

[EugeneHiihtaja]

Hello !

1. In normal Cortex-M4  exists Auxiliary Control Register, ACTLR what user for enable/disable WriteBuffer.

#define CPU_REG_SCnSCB_ACTLR ( * (( uint32_t * )( 0xE000E008U )))
#define CPU_REG_SCnSCB_ACTLR_DISDEFWBUF ( 0x00000002U )

I think in case of K82 this WriteBuffer is missing because you have other set of caches -  LMEM.

And all functionality is implemented in fsl_cache.h/fsl_cache.c files.

In my design I using MPU module and interesting what is proper sequence to enable all caches ?

/*  SYSMPU Initialisation & Enable. */
SYSMPU_Init(SYSMPU, &userConfig1);

L1CACHE_EnableCodeCache();
L1CACHE_EnableCodeCacheWriteBuffer(true);
L1CACHE_EnableSystemCache();

Is this right order ?

2. Should I invalidate all caches and disable write buffer if I disable MPU  ?

3. Is any invalidation or temporary disabling are need if I put MCU to low power mode LLS3 ?

4. Do I undestand right, for achieve even better performance I should enable 

FTFx_CACHE_Init() as well ?

Should I set also FTFx_CACHE_PflashSetPrefetchSpeculation(ftfx_prefetch_speculation_status_t )

for enable prefech for code and data  ? Or it is enabled by default ?

When this cache should be enabled ? Before of after L1 caches ?

5. Is any other caches available on K82 to accelerate performance ?

6.  in SDK file fsl_ftfx_cache.c you have used a lot of code like this :

/* Memory barriers for good measure.
* All Cache, Branch predictor and TLB maintenance operations before this instruction complete */
__ISB();
__DSB();

But why ISB executed before DSB ?

In all ARM documentation it is recommended other sequence:

__DSB()

__ISB()

Just interesting to know.

Regards,

Eugene

[FelipeGarcia]

Hi Eugene,

The lines you mentioned are not referring to different caches, but they are doing different things.

As you can see FTFx_CACHE_ClearCachePrefetchSpeculation(&s_cacheDriver, false); uses the FMC driver. The Flash Memory Controller (FMC) is a memory acceleration unit used to enhanced flash performance.

On the other hand L1CACHE_InvalidateCodeCache(); is invalidating code cache using LMEM controller as you mentioned before.

Hope this helps!

Best regards,
Felipe

-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

[EugeneHiihtaja]

Hi Felipe !

Could you clarify one more detail.

1.

I'm using for nonvolatile data storage last 2 sectors on flash space. And it is no any code run is expected for that area in any conditions.

Should I really use FTFx_CACHE_ClearCachePrefetchSpeculation(&s_cacheDriver, false); / true and L1CACHE operation in this case ?

2.

Should I really call API for FTFx_CACHE_PflashSetPrefetchSpeculation() for code and data or after initialization prefetch is set ON for code and data by default. Or how properly initialize FMC cache for have max gain for flash performance ?

Regards,

Eugene

[FelipeGarcia]

Hi Eugene, 

1. The FMC prefetch speculation buffer allow the FMC to respond to flash accesses faster. Cache prefetch is not related to avoid code execution in certain flash areas.

2. The FMC cache and prefetch buffers are enabled by default. Both instructions and data accesses can trigger a speculative prefetch cycle.

Please check the following application note.

Optimizing Performance on Kinetis K-series MCUs

Have a great day,
Felipe

-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

[EugeneHiihtaja]

Hi Felipe !

I'm using MPU and configure memory regions in RAM/ROM where is execution enabled. It work fine for  limit/enable User privileged software.

If FMC cache is enabled by default, have it sense to take care about it at all in areas where execution is not expected ?

Like in my case, when last 2 flash sectors is used for store some data.

I can easily write 4 bytes aligned chunk at once even I think it should be 16 bytes lines only. Or atomic write unit to flash memory is 4 bytes ?

By the way how-to possible to see all NXP's application notes for K82 MCU ?

Generic page Arm® Cortex® -M4|Kinetis K82 150 MHz Secure MCUs|NXP  dosn't have link  AN4547. 

Regards,

Eugene

[FelipeGarcia]

Hi Eugene,

• FMC cache will just enhances flash accesses so I wouldn't worry about those areas.
• Writing to flash requires the start address to be 4-byte aligned but you could specify the number of bytes you want to write just making sure the length is 4-byte aligned.

• AN4745 is located in K70 Application Notes but it works for all Kinetis devices. You can access specific K82 application notes in the Documentation section in K82 page.

I hope this helps.

Best regards,
Felipe

-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

[EugeneHiihtaja]

Hi Felipe !

Does NXP has page where possible to see all ANxxx in sequential order ?

Looks like it is exists more K82 relative AppNotes then mentioned on K81 Doc pages.

But it would be nice to know and read all of them.

Regards,

Eugene

[FelipeGarcia]

Hi Eugene,

Unfortunately, there is no site where you could see all the available application notes. You need to look for them on specific device page.

Best regards,

Felipe

[FelipeGarcia]

Hi Eugene,

1. There is no specific order, I suggest you to first enable the caches and then the write buffers. You could also enable L1CACHE_EnableSystemCacheWriteBuffer(true);

2. No, you don't need to deactivate caches.

3. According to the reference manual caches are not affected by LLS3 mode, please refer chapter 9.3.

4,5. As you know this device includes two 8 KB of combined data/ instructions cache. When you use the fsl_ftfx_cache.c you are not enabling a different cache, is just a different driver.

6. To my understanding in this specific case __ISB(); and __DSB(); functions don't need to be in an specific order because we are not working in a complex operating system where a context switch is needed.

ISB instruction flushes the pipeline and DSB ensures all explicit data transfers before the DSB are complete before any instruction after the DSB is executed.

Hope this helps.

Best regards,

Felipe

[EugeneHiihtaja]

Hi Felipe !

Thank you !

Could you clarify a bit about few answers.

1. Is exists on K82 register ACTLR ,what used for enable/disable WriteBuffer,  ?

   or LMEM driver is cover whole cache functionality.

4. Can I completely drop FTFx_CACHE API usage from pflash SDK example ( it demonstrate flash erase/read/write API)

   and use LMEM API  e.g Code/System caches only ?

  Or what is relation  between those 2 caches ?

Thank you !

Regards,

Eugene

[FelipeGarcia]

Hi Eugene,

1. For enable/disable write buffer you should use LMEM_PCCCR and LMEM_PSCCR registers for code and system cache respectively.

4. Yes, I'd recommend you to use LMEM driver instead for a better implementation.

Have a great day,
Felipe

-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

[EugeneHiihtaja]

Hi Felipe !

But how I should understand those few lines in pflash example in K82 latest SDK:

/* Post-preparation work about flash Cache/Prefetch/Speculation. */
FTFx_CACHE_ClearCachePrefetchSpeculation(&s_cacheDriver, false);

#if defined(FSL_FEATURE_HAS_L1CACHE) && FSL_FEATURE_HAS_L1CACHE
L1CACHE_InvalidateCodeCache();
#endif /* FSL_FEATURE_HAS_L1CACHE */

It looks like this is 2 independent caches ?

Or this is just example what demonstrate  code cache cleaning ?

Regards,

Eugene