K64F instruction cache operation

[adriangogu]

Hello,

I am using FRDM-K64F module.

Found in ARM documentation a note telling: "A small caching component is present in the Cortex-M3 and Cortex-M4 processors to accelerate flash memory accesses during instruction fetches."

Referring to this note I would ask whether such instruction cache component is implemented within K64 microcontroller.

Could you please indicate documentation describing the operation / configuration of the mentioned instruction cache ?

For application code profiling accuracy, I would be interested to know if instruction cache usage can be disabled/bypassed ?

Thank you.

Best Regards,

Adrian

[adriangogu]

Found instruction cache described in K64 Sub-Family Reference Manual, chapter 28, Flash Memory Controller (FMC).