Hello,
I have worked with the product engineers in the past on other Kinetis devices and found that the disparity between the typical room IDD data and the max IDD can be explained by the condition of the testing. The typical values are characterized at 25C, 3.0 Volts. The maximum represent the maximum IDD limit of a large sample of silicon at the maximum junction temperature with some extra guardband. This maximum will never be exceeded if the MCU operating conditions are within temp and voltage specification.
If the temperature extremes your product will see do not go much above a 70 C (160 F) then the IDD of the device will be much less than the maximum.
If you look at the IDD specs of VLPS and note the Max of the room temp is 1.3 ma and the spec increases to 7.6 ma for 70C. This is in the same realm of increase seen in the VLPR IDD spec.
The last thing I would like to mention is that the K61 is a highly integrated MCU with large amounts of FLASH, RAM and many peripherals including DDR, Ethernet and USB. All of these features become a part of the IDD limits in an all-clock gates on specification. As you turn off the clocks modules that cannot work at VLPR, USB, Ethernet, DDR controller, etc, and disable the pin controls of large number of unused pins for the same modules the IDD numbers will decrease accordingly.
I hope this helps.
Regards,
Philip