Hangs up here:
while (MCG_S & MCG_S_IREFST_MASK){}; // wait for Reference clock Status bit to clear
Tried all J9/J6 combinations, still halts there.
I am reasonably sure, this being only my second board from Freescale Kinetis Tower series, that I am NOT THE ONLY ONE
this has happened to, and that Freescale is aware, has a solution etc etc etc.
While I see the humour in this, the management here fails to see the funny side of two 'Highly integrated' 'Out of the Box' functional
kits to 'speed our time to market' that prove to be bug ridden disasters.
I would have thought the safest way forward would be to use the on board xtal etc - not so!
calling info
#define K60_CLK | 1 | |
#define REF_CLK | XTAL8 /* value isn't used, but we still need something defined */ | |
#define CORE_CLK_MHZ | PLL96 | /* 96MHz is only freq tested for a clock input*/ |
Hi Richard Lowes,
What is the part number of your demo board, TWR-K60DN512 or TWR-K60D100M?
And which demo project are you running?
Richard
See page 9 of http://www.utasker.com/docs/KINETIS/uTaskerV1.4_Kinetis_demo.pdf
for clocking/jumper settings.
If you work with Ethernet you need to use the 50MHz source from the TWR_SER board.
See also http://www.utasker.com/kinetis/TWR-K60F120M.html
for binaries that you can use to check the operation, including KBOOT compatible USB-HID and UART loading with USB-MSD composite capability in parallel.
Regards
Mark
Hi,
I have moved your question to the community where you will get support on your issue.
If you have more questions related to this Freescale Product part then please post them in this community where This thread was moved.
Have a nice day.
Best Regards,
Garabo