Currently I am writing software for a KL05 microcontroller using Kinetis Design Studio and the Processor Expert Code Generation Tool. I'm facing an issue in my design with conflicting interrupts.
One interrupt is for servicing a SPI transaction and the other is an either-edge sensitive interrupt on PORTB. The PORTB interrupt is set to 3 (the lowest level of priority you can go in Cortex-M0) and the SPI interrupt is set to 0 (the highest priority). I'm using 2 different GPIOs toggled at the beginning and end of each interrupt to know whether or not the interrupt is active.
The issue is apparent when looking at the following oscilloscope screenshot:
(Ignoring the light blue signal in this picture, the yellow is the SPI clock line, the pink is the "active" signal of the SPI receive interrupt, and the green is the "active" signal of the PORTB interrupt.)
Even though the SPI interrupt is set to the higher priority, there are times (like in the picture) when the PORTB interrupt occurs in the middle of the transaction, that the SPI interrupt is not allowed to interrupt the PORTB interrupt. It's my understanding that since the SPI interrupt is set to the higher priority, it should be allowed to preempt the PORTB interrupt. I have done plenty of browsing of the KL05 Reference Manual as well as the ARMv6-M Reference Manual and I can't come to any conclusion. Am I doing something wrong or is my assumption incorrect?
Any help would be appreciated, thanks.
