Hi Qi,
During all stop modes, clocks to the UART module are halted.
No UART module registers are affected in Stop mode.
The receive input active edge detect circuit remains active in Stop mode. An active edge on the receive input brings the CPU out of Stop mode if the interrupt is not masked (UART_BDH[RXEDGIE] = 1).
Because the clocks are halted, the UART module resumes operation upon exit from stop, only in Stop mode. Software must ensure stop mode is not entered while there is a character being transmitted out of or received into the UART module.
So, it need to set UART_BDH[RXEDGIE] = 1 before the core enter into the STOP mode.
Wish it helps.
Have a great day,
Ma Hui
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