Timestamping events in the code

[samyuktaramnath]

Hello all,

I am using a K53 tower Freescale Evaluation board.

I need to time stamp a particular event in the code (A data variable is filled), and would like to know if this is possible and if so, how I would go about doing it.

Thank you!

[EarlOrlando]

Dear Samyukta,

Are you using a RTOS or is your project in baremetal?

Regards,

Earl.

[samyuktaramnath]

Dear Mr. Earl,

I tried using the RTC to read the number of clock cycles. I used the RTC_TPR register. I Initialized the RTC and then read the value of the RTC_TPR register before loading the data variables and after loading the data variables.

I am trying to establish communication between an analog chip and the K53 microcontroller. I have done so using SPI link, but I want to confirm that the Analog chip (slave) is sending data at the rate I have asked it to. I have given a clock of 1000 kHz from the master for SPI communication, and I should be getting data at a rate of 2000 words per second from the slave. Now to achieve the timestamping, I have read the RTC clock at the event of receiving a word in the code. If the RTC clock is 32kHz, I should be able to correctly detect a data rate of 2000 words per second, right?

However, the time interval according to the RTC to get 500 data variables is much less than 0.25 seconds. It is around 0.0175 seconds.

Am I doing something wrong, either in using an RTC clock less than the SPI master clock (even though I need to detect the event as received word, not received byte), or in the way I am using the RTC clock?

The code I have used is below:

to initialize the RTC

void rtc_init(uint32 seconds, uint32 alarm, uint8 c_interval, uint8 c_value, uint8 interrupt)

{

  int i;

  /*enable the clock to SRTC module register space*/

  SIM_SCGC6 |= SIM_SCGC6_RTC_MASK;

  /*Only VBAT_POR has an effect on the SRTC, RESET to the part does not, so you must manually reset the SRTC to make sure everything is in a known state*/

  /*clear the software reset bit*/

  RTC_CR  = RTC_CR_SWR_MASK;

  RTC_CR  &= ~RTC_CR_SWR_MASK; 

  /*Enable the interrupt*/

  if(interrupt)

    enable_irq(66);

  /*Enable the oscillator*/

  RTC_CR |= RTC_CR_OSCE_MASK;

  /*Wait to all the 32 kHz to stabilize, refer to the crystal startup time in the crystal datasheet*/

  for(i=0;i<0x600000;i++);

  /*Set time compensation parameters*/

  RTC_TCR = RTC_TCR_CIR(c_interval) | RTC_TCR_TCR(c_value);

  /*Configure the timer seconds and alarm registers*/

  RTC_TSR = seconds;

  RTC_TAR = alarm;

  RTC_TPR = 0;

  /*Enable the counter*/

  RTC_SR |= RTC_SR_TCE_MASK; 

}

In main module, after SPI initialization:

    time_initial= RTC_TPR;

    time_initial_sec = RTC_TSR;

    // test single byte transmission

    while(j<500){

  //for (j=0;j<4;j++){

    for (i=0;i<=11;i++){

      data[j] = reg_read(0x00000000);

    //I2C0_D = data;

    //I2C0_A1 = datain;

      time = RTC_TPR;

      time_sec = RTC_TSR;

   // printf("dataout: %x\ndatain: %x\ntime: %x\nTimeDirect: %x\n\n",data,datain,*ticky,time);

      j++;

   //  if(j==500)

     // printf("500!\n");

    }

    //printf("%d\n",j);

    reg_Write(0x40000000);

  }

  printf("initial time = %d\nintial sec = %d\nFinal Time =%d\nFinalTimeSec = %d\n\n",time_initial,time_initial_sec, time,time_sec);

}

Where reg_read and reg_Write are used to read and write from and to 32 bit words respectively.

[EarlOrlando]

If the timestamp is only to know the correct speed why don't you see the SPI signals in an oscilloscope?

And answering your questions. Yes, the RTC configuration is OK. And yes, you should be able to count every 1/32768 Hz = 30.51 us by reading the register RTC_TPR.

What is the printf printing?

Regards,

Earl.

[samyuktaramnath]

Thank you for your reply.

I have seen the SPI signals in an oscilloscope. The data rate it shows is not correct. I should get 2000 words per frame, but I am getting much less. I am checking groups of 12 times the slave select goes low. (That constitutes one frame.) I am getting around 50-100 frames per second where I should be getting 2000. Moreover, this doesn't change with the change in output data rate.

In the RTC, it prints 370 cycles. Which means, the time taken for 500 data variables to be filled is around 0.0113 s, so the time it takes for 2000*12 (2000 frames - each frame contains 12 words), it takes around 0.54 seconds. That's faster than 2000 words per second data rate I was going for.

Moreover, when I change the data rate output from the AFE to 16000 frames per second, it still gives around the same number of cycles.

I tried time stamping with PIT timer. In the ISR, i incremented a timer, and kept a load value of around 4000. So it goes into the ISR every 80 us. I have a variable which increments in the ISR. After the code is done, I print the value of the incremented variable to get the number of clock cycles passed. Around 71 cycles usually pass, which gives a time of (2000*12/500)*71*(80 us) = 0.27 seconds. This again doesn't change with the output data rate. 

Someone had mentioned that measuring throughput would give a high rate of error - however, I assumed that it would atleast show an output data rate less than what I want from the AFE, not much greater.

Any further suggestions would be welcome.

[EarlOrlando]

Could you please attach your clock and SPI configurations?

Regards,

Earl.

[samyuktaramnath]

Hello Earl,

I am sorry for the delay.

The SPI and clock configurations are shown below :

  SPI0_MCR = SPI_MCR_MSTR_MASK |

              SPI_MCR_DCONF(0x00) |

                SPI_MCR_CLR_RXF_MASK |

                SPI_MCR_CLR_TXF_MASK |

                SPI_MCR_PCSIS(63)|

                SPI_MCR_HALT_MASK | //halts transfers

               (SPI_MCR_MDIS_MASK & 0x00);//|//| //enables module clocks

               // SPI_MCR_CONT_SCKE_MASK; //continuous clock             

  SPI0_CTAR0 = ((SPI_CTAR_DBR_MASK & 0x00)) |

                  SPI_CTAR_FMSZ(0x07) |

                    SPI_CTAR_PDT(0x00) |

                    SPI_CTAR_BR(0x03) |

                    (SPI_CTAR_CPHA_MASK) |

                      SPI_CTAR_PBR(0x00)|

                    (SPI_CTAR_CPOL_MASK);

  SPI0_MCR &= 0xfffffffe ; //start transfers again

[EarlOrlando]

Hello Samyukta,

I think that the problem could be in the clock configurations. May be you are assuming a bus clock frequency but we need to ensure that. Could you please share your clock configurations?

Regards,

Earl.

[samyuktaramnath]

Dear Mr. Earl

The project is baremetal.

Regards,

Samyukta