Sorry for asking this basic question. I am very new to this area. My board is KL05Z.
From the reference manual, the duty cycle is determined by "CnV". so I simply added the following lines to LED_Blink.c (before the while loop).
However, this did not work. When I run this piece of code in the board, it throws me to HardFault_Handler.
TPM0_C0V = 1;
TPM0_C1V = 1;
TPM0_C2V = 1;
TPM0_C3V = 1;
TPM0_C4V = 1;
while(1)
{
Delay(200000);
LED1_TOGGLE;
Delay(200000);
LED2_TOGGLE;
Delay(200000);
LED3_TOGGLE;
}
What's the proper way of setting the duty cycles in PWM? I attached this piece of code in MKL05Z4.h, Hopefully it is easier for people with experience to look at.
Thanks a lot!
/** TPM - Peripheral register structure */
typedef struct TPM_MemMap {
uint32_t SC; /**< Status and Control, offset: 0x0 */
uint32_t CNT; /**< Counter, offset: 0x4 */
uint32_t MOD; /**< Modulo, offset: 0x8 */
struct { /* offset: 0xC, array step: 0x8 */
uint32_t CnSC; /**< Channel (n) Status and Control, array offset: 0xC, array step: 0x8 */
uint32_t CnV; /**< Channel (n) Value, array offset: 0x10, array step: 0x8 */
} CONTROLS[6];
uint8_t RESERVED_0[20];
uint32_t STATUS; /**< Capture and Compare Status, offset: 0x50 */
uint8_t RESERVED_1[48];
uint32_t CONF; /**< Configuration, offset: 0x84 */
} volatile *TPM_MemMapPtr;
/* TPM - Register accessors */
#define TPM_SC_REG(base) ((base)->SC)
#define TPM_CNT_REG(base) ((base)->CNT)
#define TPM_MOD_REG(base) ((base)->MOD)
#define TPM_CnSC_REG(base,index) ((base)->CONTROLS[index].CnSC)
#define TPM_CnV_REG(base,index) ((base)->CONTROLS[index].CnV)
#define TPM_STATUS_REG(base) ((base)->STATUS)
#define TPM_CONF_REG(base) ((base)->CONF)
/* TPM - Register instance definitions */
/* TPM0 */
#define TPM0_SC TPM_SC_REG(TPM0_BASE_PTR)
#define TPM0_CNT TPM_CNT_REG(TPM0_BASE_PTR)
#define TPM0_MOD TPM_MOD_REG(TPM0_BASE_PTR)
#define TPM0_C0SC TPM_CnSC_REG(TPM0_BASE_PTR,0)
#define TPM0_C0V TPM_CnV_REG(TPM0_BASE_PTR,0)
#define TPM0_C1SC TPM_CnSC_REG(TPM0_BASE_PTR,1)
#define TPM0_C1V TPM_CnV_REG(TPM0_BASE_PTR,1)
#define TPM0_C2SC TPM_CnSC_REG(TPM0_BASE_PTR,2)
#define TPM0_C2V TPM_CnV_REG(TPM0_BASE_PTR,2)
#define TPM0_C3SC TPM_CnSC_REG(TPM0_BASE_PTR,3)
#define TPM0_C3V TPM_CnV_REG(TPM0_BASE_PTR,3)
#define TPM0_C4SC TPM_CnSC_REG(TPM0_BASE_PTR,4)
#define TPM0_C4V TPM_CnV_REG(TPM0_BASE_PTR,4)
#define TPM0_C5SC TPM_CnSC_REG(TPM0_BASE_PTR,5)
#define TPM0_C5V TPM_CnV_REG(TPM0_BASE_PTR,5)
#define TPM0_STATUS TPM_STATUS_REG(TPM0_BASE_PTR)
#define TPM0_CONF TPM_CONF_REG(TPM0_BASE_PTR)
/* TPM1 */
#define TPM1_SC TPM_SC_REG(TPM1_BASE_PTR)
#define TPM1_CNT TPM_CNT_REG(TPM1_BASE_PTR)
#define TPM1_MOD TPM_MOD_REG(TPM1_BASE_PTR)
#define TPM1_C0SC TPM_CnSC_REG(TPM1_BASE_PTR,0)
#define TPM1_C0V TPM_CnV_REG(TPM1_BASE_PTR,0)
#define TPM1_C1SC TPM_CnSC_REG(TPM1_BASE_PTR,1)
#define TPM1_C1V TPM_CnV_REG(TPM1_BASE_PTR,1)
#define TPM1_STATUS TPM_STATUS_REG(TPM1_BASE_PTR)
#define TPM1_CONF TPM_CONF_REG(TPM1_BASE_PTR)