How to do the clock initialization

[mishra_shrutiki]

How to initialize the clock for MK24F12(kinetic controller) in IAR workbench. 

[Robin_Shen]

Please download MCUXpresso Config Tools - Pins, Clocks, Peripherals.

Using Clocks Tool

For a graphical representation of the MCU clock tree system and interactive user controls as well as assistance with system fine-tuning.

Best Regards,

Robin

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[mjbcswitzerland]

Hi

If you want to understand MCG details check out http://www.utasker.com/kinetis/MCG.html

Code for TWR-K24F120M is included in https://github.com/uTasker/uTasker-Kinetis

Assuming you want to use the PLL to generate 120MHz (and max. speed clocks) the configuration is:

#define OSC_LOW_GAIN_MODE                                        // use low gain oscillator mode since there is not crystal loading in the circuit
#define CRYSTAL_FREQUENCY    8000000                             // 8 MHz crystal
#define _EXTERNAL_CLOCK      CRYSTAL_FREQUENCY
#define CLOCK_DIV            2                                   // input must be divided to 2MHz..4MHz range (/1 to /24)
#define CLOCK_MUL            30                                  // the PLL multiplication factor to achieve operating frequency of 120MHz (x24 to x55 possible)
#define FLEX_CLOCK_DIVIDE    3                                   // 120/3 to give 40MHz
#define FLASH_CLOCK_DIVIDE   5                                   // 120/5 to give 24MHz

Code for this is (not IAR specific because compatible with all compilers):

    MCG_C1 = (MCG_C1_CLKS_EXTERN_CLK | MCG_C1_FRDIV_VALUE);              // switch to external source (the FLL input clock is set to as close to its input range as possible, although this is not absolutely necessary if the FLL will not be used)
    while ((MCG_S & MCG_S_OSCINIT) == 0) {                               // loop until the crystal source has been selected
    }
    while ((MCG_S & MCG_S_IREFST) != 0) {                                // loop until the FLL source is no longer the internal reference clock
    }
    while ((MCG_S & MCG_S_CLKST_MASK) != MCG_S_CLKST_EXTERN_CLK) {       // loop until the external reference clock source is valid
    }
    MCG_C5 = ((CLOCK_DIV - 1) | MCG_C5_PLLSTEN0);                        // now move from state FEE to state PBE (or FBE) PLL remains enabled in normal stop modes
    MCG_C6 = ((CLOCK_MUL - MCG_C6_VDIV0_LOWEST) | MCG_C6_PLLS);          // set the PLL multiplication factor
    while ((MCG_S & MCG_S_PLLST) == 0) {                                 // loop until the PLLS clock source becomes valid
    }
    while ((MCG_S & MCG_S_LOCK) == 0) {                                  // loop until PLL locks
    }
    SIM_CLKDIV1 = (((SYSTEM_CLOCK_DIVIDE - 1) << 28) | ((BUS_CLOCK_DIVIDE - 1) << 24) | ((FLEX_CLOCK_DIVIDE - 1) << 20) | ((FLASH_CLOCK_DIVIDE - 1) << 16)); // prepare bus clock divides
    MCG_C1 = (MCG_C1_CLKS_PLL_FLL | MCG_C1_FRDIV_1024);                  // finally move from PBE to PEE mode - switch to PLL clock
    while ((MCG_S & MCG_S_CLKST_MASK) != MCG_S_CLKST_PLL) {              // loop until the PLL clock is selected
    }
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Simulation, showing clock speeds achieved:

Regards

Mark

Complete Kinetis solutions for professional needs, training and support: http://www.utasker.com/kinetis.html
Kinetis K21/K22/K24:
- http://www.utasker.com/kinetis/TWR-K21D50M.html
- http://www.utasker.com/kinetis/TWR-K21F120M.html
- http://www.utasker.com/kinetis/FRDM-K22F.html
- http://www.utasker.com/kinetis/TWR-K22F120M.html
- http://www.utasker.com/kinetis/BLAZE_K22.html
- http://www.utasker.com/kinetis/tinyK22.html
- http://www.utasker.com/kinetis/TWR-K24F120M.html