How long is the default bus frequency?

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How long is the default bus frequency?

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markbrinkman
Contributor II

Using MK20DN512VMD10, on a POR or the assertion of RESET (while powered) what is the bus clock frequency? Using register defaults I believe it to be 20.19MHz. This question arose after reading section '6.2.4 Reset Pin' in the reference manual about RESET being active for at least 128 bus clock cycles. Can this time occur before VDD reaches 3.3V?

thanks

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kerryzhou
NXP TechSupport
NXP TechSupport

Hi MARK BRINKMAN,

    In default, the MK20DN512VMD10 is using the 32.768 IRC as the clock source, the clock mode is FEI, FLL default factor is 640.

So, the default bus clock is 32.768*640=20.971Mhz.

   About the POR sequence, you can refer to this post, there has a picture, you can know the detail kinetis POR sequence, FLL working and the reset pin relationship.

https://community.nxp.com/docs/DOC-332014

 

Wish it helps you!

If you still have question, please let me known.

Have a great day,
Kerry

 

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markbrinkman
Contributor II

Thanks Kerry,

I think you meant 20.971MHz instead of 20.971KHz

I do have follow up questions:

1. The post you referenced states that initialization takes place after the Reset_b pin is released while the following section in the MK20DN512VMD10 reference manual states that internal initialization is done while the Reset_b pin is asserted. Can you explain this contradiction?

2. To be clear the duration of the aforementioned 128 bus clock cycles, at 20.971MHz, is at least 6.1us. Is this time part of T3 in the posts picture?

Thanks

Mark

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kerryzhou
NXP TechSupport
NXP TechSupport

Hi Mark Brinkman,

   Yes, it is 20.971MHz, my mistyping.

   pastedImage_2.png

     You can consider the T3 on the above picture should be at least 128 bus clock cycles.

     That document is from the KE series. in the K series, please refer to the reference manual, the RESET pin is driven low by the MCU for at least 128 bus clock cycles and until flash
initialization has completed.

     The picture is give your a reference. You can consider T3 should at least 128 bus clock, it is for the flash initialization.

      Wish it helps you!

      If you still have question, please let me know!


Have a great day,
Kerry

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