Help with setting up ADC channels / PIT / PDB / DMA

[ryanjohnson]

In my setup, I will be using both ADC channels as follows:

ADC0 has 3 channels which are sampled at 100 Hz each.

ADC 1 has 2 channels which are sampled at ~30 KHz each.

For the slow ADC0 channels, I'd like every 10 ms to sample each of the 3 inputs and DMA the result into a 3-by-10 array (so I'd essentially get an interrupt every 100 ms with 10 new samples for each channel).

For the faster ADC1 channels, the operation is essentially the same except there are only two channels and my DMA buffers will be much larger (say 256 samples for each channel).

My question is in using the PIT and/or PDB modules to drive these. I've done single channel sampling with both PIT and PDB, but in attempting to move to the 'scan' method as described in AN4590 I'm not sure if I should be using one or or the other (or both).

Based on other postings here, I think that for the high speed sampling, it makes sense to setup the PIT to produce a 30 KHz interrupt which feeds into the PDB trigger. The PDB then generates two pulses -- one is offset by 0 clocks and triggers the reading from the first ADC1 channel, and the second is offset by ~10us and triggers sampling the second ADC1 channel.

For the slower sampling, I'm not sure yet what makes the most sense to do.

Any thoughts or tips are appreciated!

Thanks, Ryan

[Hui_Ma]

Hi Ryan,

For the ADC0 is slow scan channel, I would suggest to use PIT timer with 3.3ms to software trigger ADC0, in PIT timer interrupt service routine, it can modify the channel number one by one.

Customer can refer below PIT interrupt service routine about software trigger ADC0 conversion:

PE_ISR(PIT0_ISR)

{

// NOTE: The routine should include actions to clear the appropriate

//       interrupt flags.

    PIT_TFLG0 |= PIT_TFLG_TIF_MASK;

if (counter == 0)

{    ADC0_SC1A = ADC_SC1_ADCH(23);

}

else if (counter == 1)

{

     ADC0_SC1A = ADC_SC1_ADCH(24);

}

    while((ADC0_SC1A & ADC_SC1_COCO_MASK) == 0);                                //Wait for sample conversion to complete

    ADC0_Result[counter] = ADC0_RA;

  counter++;

}

For the ADC1 fast scan channel, customer can use PDB module ping-pong mode, just as your description.

Wish it helps.

B.R.

Ma Hui

[ryanjohnson]

Thanks Ma,

Your described method is pretty much the road I've been going down, except for the high speed sampling I want to use DMA since the rates are so high.

So one question regarding using DMA, is it possible for two DMA channels to transfer from ADC1 to memory, one channel reading ADC1_RA and the other reading ADC1_RB, or do I need to use the 'channel scan' method described in AN4590? I was hoping that I could configure the PDB to fire at 30 KHz and produce two triggers: trigger A with a delay of 0 and trigger B with a delay of 15us. PDB trigger A would trigger ADC1 channel select A, recording to ADC1_RA and PDB trigger B would trigger ADC1 channel select B, recording to ADC_RB.

It seems like the PDB & ADC blocks are designed to do this, but I don't know if I can tie this into DMA.

-- Ryan

[Hui_Ma · Accepted solution]

For ADC1 is only one DMA trigger source, that could not assign to two DMA channels.

There is only one DMA channel availabe for ADC1 module.

So, customer need to use AN4590 provide way to link DMA channel, one channel to move ADC1 result, the link channel to modify previous source address.

I just calculate DMA response trigger to finsh transfer will take almost 20 system cycles, two DMA transfer will take almost 40 system cycles.

If system clock is 100MHz, the DMA transfer will take 0.4us.

I think the DMA transfer is not the bottleneck, in fact, the ADC conversion time need be balance to match the application.

Wish it helps.

[ryanjohnson]

That's good information. Thanks for the help!