I want to reduce or eliminate the possibility of resets due to noise on the RESET_b pin of the MCU that I am using (MKE16F512VLH16, PTA5, PIN 63)
Will a simple conversion of PTA5 to a GPIO accomplish this? If so, will I still be able to debug my code using SWD via P&E Multilink Universal USB hardware and MCUExpresso IDE v10.0.2 [Build 411] [2017-07-11]?
Alternatively, I have considered enabling the digital glitch filter on the RESET_b PIN, but it is not clear if this should be done via PORT control or the RCM. Are these two methods independent?
If implementing a glitch filter on RESET_b, then how and where in the code can I do this so as not ending up in an infinite loop of resetting? This is what happened when I tried to implement the glitch filter in main() using simple writes to the required PORT control registers (DFWR, DFCR, and DFER)
Thank you kindly for your guidance.
I think the Reset_b(PTA5) has it's own independent passive filter circuit, the passive filter is enabled during/after Reset b in default, so it is useless to set the DFWR, DFCR, and DFER registers.
I copy the table from RM of KE1xFP. In default state, the Reset_b(PTA5) is pull-up and passive filter enabled.
Regarding you abnormal reset issue, I suggest you use a RC circuit for the Reset_b pin.
Pls note that it is NOT software issue which reset the processor.
Thank you for your reply. If you look at the PORT I/O pin structure (pg 783 of the RM), I believe that the passive filter and the glitch filter are independent.
I am using an RC filter on RESET_b (0.1uF x 10kohm) and have no trouble with resets until I insert code main to write to DFWR, DFCR, and DFER. When I remove this code, everything works as expected.
Does any of this information change your opinion? Thanks again for your time!
Thank you for pointing out that the "glitch filter" and "passive filter" are independent modules.
You said that the KE16 works fine if you do not set up the DFWR, DFCR, and DFER registers, I suppose that your problem is not related to Reset pin feature, the software leads to the Reset issue.
Pls note the line "Changing the filter clock source must be done only when all digital filters are disabled", before you write the PORTx_DFCR and PORTx_DFWR, you should clear PORTx_DFER register. Pls have a try.