When PTB0, PTB1 don't be set, FTM0 PWM don't work.
and when input pulses in GPIO mode are put to PTB0, FTM0 stops.
When PTB0, PTB1 are set to GPIO and no input pulse, FTM0 work.
FTM0 symtom is really abnormal.
What is the problem?
MCU: MK10DN32VLF5
Compiler: IAR EWARM ver 6.5
Code is below:
<Initialization>
/* FTM0 ----------------------------------------------------------------- */
SIM_SCGC6 |= SIM_SCGC6_FTM0_MASK;
/* PTC2(Pin 35) PWM_TO_DAC */
PORTC_PCR2 &= ~PORT_PCR_MUX_MASK;
PORTC_PCR2 |= PORT_PCR_MUX(4); // FTM0_CH1
/* Write Protection Disable */
FTM0_MODE |= FTM_MODE_WPDIS_MASK;
/* FTM Enable */
FTM0_MODE |= FTM_MODE_FTMEN_MASK;
/* Counter run in BDM mode */
/* FTM Counter Functional mode */
FTM0_CONF |= FTM_CONF_BDMMODE(3);
/* Set PWM frequency; MODULO = Fclk/Fpwm */
/* 20kHz, 50000000 / 20000 = */
FTM0_MOD = 2500; // 20kHz
FTM0_CNTIN = 0x00; // Counter Initial value
/* 1 Enhanced PWM synchronization is selected. */
FTM0_SYNCONF |= FTM_SYNCONF_SYNCMODE_MASK;
/* CTNMAX = 1 - PWM update at counter in max. value */
FTM0_SYNC |= FTM_SYNC_CNTMAX_MASK;
/* Disable all channels outputs using the OUTPUT MASK feature.*/
DISABLE_PWM_OUTPUT();
FTM0_COMBINE = FTM_COMBINE_SYNCEN0_MASK | FTM_COMBINE_COMBINE0_MASK ;
/* polarity setting, 3ppa driver high sides are active low */
FTM0_POL = FTM_POL_POL1_MASK;
/* Initial setting of value registers */
FTM0_C1V = 0;
/* SWSYNC = 1 - set PWM value update. This bit is cleared automatically */
FTM0_SYNC |= FTM_SYNC_SWSYNC_MASK;
/* Main loop */
/* ELSnB:ELSnA = 1:0 Set channel mode to generate positive PWM */
FTM0_C1SC |= FTM_CnSC_ELSB_MASK ;
FTM0_MODE |= FTM_MODE_INIT_MASK;
/* Set system clock as source for FTM0 (CLKS[1:0] = 01) */
FTM0_SC |= FTM_SC_CLKS(1); // System clock
<background>
DutyCycle = 1250;
FTM0_C1V = DutyCycle; // 825(PWM 33%) => 0.9V => 3A
FTM0_PWMLOAD = FTM_PWMLOAD_LDOK_MASK; // LDOK (set value)
