Hi, all,
Regarding the FTM driving clock, it is dependent on the FTM clock source and prescaler, in other words, the FTM driving clock frequency equals to (FTM clock source frequency)/Prescaler.
The CLKS bits in FTM_SC register determines the FTM clock source for KEA128 chip:
CLKS bits clock source
00 FTM disabled
01 system clock source
10 Fixed frequency clock
11 External clock source
Pls refer to Figure 5-3. FTM and PWT clock generation in the KEA128RM.pdf for the detailed FTM clock source.
When the CLKS=01, the system clock source is selected, in the condition, the ICSOUTCLK clock source divided by DIV3 is used as FTM clock source, DIV3 bits is specified in SIM_CLKDIV. Pls refer to the Figure 5-1. Clocking diagram in KEA128RM.pdf.
when the CLKS=10, the ICSFFCLK clcok source is selected as FTM clock source, ICSFFCLK clock source is 37.5KHz IRC or (external OSC)/RDIV, pls refer to Figure 5-1. Clocking diagram.
when the CLKS=11, the FTM clcok source are from TCLK0/TCLK1/TCLK2 pins, SIM_PINSEL0[FTM0CLKPS] select the clock source pins from the three pins. Note TCLK0/TCLK1/TCLK2 are Kea128 external signal pads, for example:
This is the pin assignment of TCLK0 pin.
79(79 LQFP) 63(63 LQFP) PTA5, RESET_b, PTA5 KBI0_P5, IRQ, TCLK0, RESET_b
In otherwords, you can connect the external clock source to the TCLK0 pin, the FTM driving clock frequency will be (TCLK0 Pin clock frequency)/Prescaler, the prescaler is defined in the FTM_SC register.
Note you should enable the FTM gate clock by setting the corresponding bit in SIM_SCGC register when you use CLKS=01 setting..
BR
Xiangjun Rong