FLL and PLL Disabled in BLPI mode

[danebouchie]

It's to my understanding that in the Bypassed Low Power Internal, the FLL and PLL are disabled. However, when I set the clock configuration I get a warning:

Description	Resource	Path	Location	Type
Warning: The PLL/FLL clock value is 0 - the clock is disabled. (Clock frequency [MHz])			Cpu/Clock frequency [MHz]	Processor Expert Problem

So, what's the actual problem with disabling both? Why am I getting this warning? BLPI mode is the only mode that allows me to use Very Low Power Mode, which is the purpose in using that as opposed to other modes. This is the only clock configuration.

[mjbcswitzerland · Accepted solution]

Hi Dane

I suspect that the warning that you are getting can be ignored since, as you know, BLPI is the same as FBI as far as the processor core is concerned.

However beware that it may be possible for perpherals to (optionally) use the FLL or PLL outputs (MCGPPLCLK/MCGFLLCLK) in FBI and maybe the warning is due to that (?).

There are some practical details at http://www.utasker.com/kinetis/MCG.html

In the case of VLPS mode I don't think that you need to worry about whether you are in BLPI or FBI since the PLL and FLL will automatically be stopped anyway.

Regards

Mark

[danebouchie]

Thanks, I guess that makes sense why the warning is there, but not necessarily why won't didn't disappear. I just check all my components and they aren't using the FLL (or PLL) clocks. I think its just PE forcing me to chose to use the PLL or FLL, and isn't smart enough to handle no PLL or FLL.