Embedded Trace Macrocell (ETM) PCB Routing Tips

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Embedded Trace Macrocell (ETM) PCB Routing Tips

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pgvoorhees
Contributor II

Hello Community,

We are planning on using ETM to aid in debugging but have found very few routing guidelines for the TRACE_D[0:3] and TRACE_CLK nets.

On the K22FX512, using a 120MHz core speed, What is:

  • The clock speed of the TRACE nets? Datasheet says the interface is limited to 50MHz but offers no guidance for determining the speed.
  • Is any particular characteristic impedance for the traces necessary?
  • Do the lines need to be length-matched?

Design guild-lines seem to be largely unavailable and the Kinetis datasheets are light on details for this particular functionality. Any help is appreciated. Thanks!

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pgvoorhees
Contributor II

The best reference I've found for this is the Segger J-Link/J-Trace manual.

J-Link Debug Probes | SEGGER - The Embedded Experts 

Chapter 17 (as of this post) called "Designing the target board for trace"

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