DATA CRC error when sending data over SDIO

[yash_bhatt1]

Hi,

I am working on FRDM-K64F and have interfaced an IO device (wifi module) over SDIO. I have configured SDIO to use ADMA2.

Below is the major flow of my program:

- Write 1000 Bytes of data (success).

- Read back 1000 Bytes of data (success) (Note: this is the first time I am reading large chunk of data since the start of program. So far data lines have been used only for writing large chunk of data).

- Read 4 bytes of data (this fails because Transaction complete flag never set)

- Write 1000 Bytes of data (fails with Data CRC error) (Interrupt status 0x200010).

I have probed the hardware  lines in the failure case of 1000 byte write and below is my observation:

- Clock: on.

- Data 0-3: no activiy.

- CMD line: Activity detected.

I have tried to do a data line reset using the SDIO_reset() api from the SDHC driver before I failure case write but I see no effect.

Please help me understand why is there no activity on the data line and what is causing Data CRC error given that the first chunk of data is successfully transmitted with the same mechanism?

Thank you

[Sabina_Bruce]

Hello ,

Hope you are doing well.

To better understand what is occurring, could you please reproduce this using an example on the SDK. I understand that you are using a third party wifi module. However, it is not clear what may be causing the data crc error. If not possible to reproduce this using an example, could you attempt to do the communication without DMA to be able to pinpoint the issue. 

Best Regards,

Sabina

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[yash_bhatt1]

Hi Sabina,

We are not able to reproduce the issue with the SD card example.

But we have noted a few observations that might help in resolving this issue:

- After the issue is encountered, Data[1:3] are stuck high, that is the next packet is only sent on D0.

  So we tried to change to single bit mode and bingo we stopped seeing the data CRC error. But this is

  not the expected behavior as there is no possible reason for the SDIO to move from 4 bit mode to 1 bit mode

  by itself after the Data CRC error.

- The issue only reproduces after a chunk greater than 64 bytes has been received, If chunks less than 64 bytes are

  received we dont see any issue.

- When the issue occurs, DMA error status register has value 0x03.

We suspect it might be something to do with data alignment for DMA or some setting we are missing here.

Hope you can help us out with this.

Thank you.

[Sabina_Bruce · Accepted solution]

Hello ,

Hope you are doing well.

Based on your latest description I found that your issue may be described in the errata.

I have provided the link so you may check the workaround described, in regards to the data block sizes. I believe your description is related to e3982.

Kinetis_K_1N83J 

Hope this helps.

Best Regards,

Sabina

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