ADC calibration values

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ADC calibration values

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billnd
Contributor IV

Hi all,

I'm using a K10 ADC in single ended mode, and trying to understand the calibration process. I have two main questions...

1. ADCx_CLPD, should this value be taken into account when generating ADCx_PG? The value seems to be generated during a self cal, but the documentation doesn't mention it.The K10 RM only says in 33.4.7..."2. Add the plus-side calibration results CLP0, CLP1, CLP2, CLP3, CLP4, and CLPS to the variable." So should CLPD also be added?

2. If storing calibration values in eeprom, so that calibration doesn't have to be re-done every boot, which registers need to be remembered? The documentation talks about 20 register stores, that makes me think its CLP0, 1, 2, 3, 4, CLPS, CLPD, OFFS, PG and MG for each ADC?

Thanks in advance,

Bill

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bryancole-b4682
NXP Employee
NXP Employee

All,

Just to clarify, the procedure desribed in the reference manual for calculating the gain register values ADCx_PG (and ADCx_MG) correctly omits CLPD (and CLMD). The gain register values are meant to subtract out any extra capacitance added during the sample phase in order to correct for capacitor mismatch. Only the capacitance that was sampled on needs to be removed. The registers CLPD and CLMD compensate for the differential bias capacitor which is not connected during the sample. Therefore, these registers should not be added to the gain register calculation.

Regards,

Bryan

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jeremyzhou
NXP TechSupport
NXP TechSupport

Hi Bilnd,

Thank you very much for your focus on Freescale Kinetis product. I'm glad to provide service for you.

1. ADCx_CLPD, should this value be taken into account when generating ADCx_PG? The value seems to be generated during a self cal, but the documentation doesn't mention it.The K10 RM only says in 33.4.7..."2. Add the plus-side calibration results CLP0, CLP1, CLP2, CLP3, CLP4, and CLPS to the variable." So should CLPD also be added?

To be honest, I've also felt a little weird about it. I'll to discuss this questions with my co-wokers later and update you if work it out.

2. If storing calibration values in eeprom, so that calibration doesn't have to be re-done every boot, which registers need to be remembered? The documentation talks about 20 register stores, that makes me think its CLP0, 1, 2, 3, 4, CLPS, CLPD, OFFS, PG and MG for each ADC?

I'd like to suggest  that you should store all calibration results which contain two seven calibration values of side gereral calibration value regsiter.

If you have any further questions, please feel free to conatct with me.

Have a nice day!

Ping

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billnd
Contributor IV

Jeremyzhou,

Thanks for your reply.

Did you get any further info regarding point 1?

Could you please clarify your response to point 2? I don't follow exactly what your are saying.

Thanks,

BillND

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jeremyzhou
NXP TechSupport
NXP TechSupport

Hi Billnd,

They've also not focused this issue before, however we all think the CPLD is added just like RM state.

The two seven calibration valuses meanCLP0[5:0], CLP1[6:0], CLP2[7:0], CLP3[8:0], CLP4[9:0], CLPS[5:0], CLPD[5:0] and CLM0[5:0], CLM1[6:0], CLM2[7:0], CLM3[8:0],CLM4[9:0], CLMS[5:0],CLMD[5:0].

You should restore all these calibration valuses.

Have a nice day!

Ping

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billnd
Contributor IV

JZ,

Thanks for the quick reply.

1. The reference manual I have...

K10P100M100SF2V2RM

Rev. 2 Jun 2012

...states that when generating PG/MG, only CLP0, CLP1, CLP2, CLP3, CLP4 and CLPS should be added. No mention of the CLPD register. Is this what you mean?

2. I now understand the two seven calibration values, that has cleared that up at least.

Cheers

BillND

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jeremyzhou
NXP TechSupport
NXP TechSupport

Hi Bilind,

Yes, no mention of the CLPD register in all RM which I've reviewed.

I made a mistake. You also need to store ADC offset correction register (OFS) besides store the two seven calibration values.
Have a great day,
Ping

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