Indeed, these status flags, like many others, are "write 1 to clear". That may seem backwards and arbitrary, but it's the way Freescale designed the hardware (and several other companies have also designed their microcontroller peripherals), and for very good reason which I'll explain in a moment....
This code is also very inefficient. It reads unnecessarily FTFL_FSTAT 3 times. Then in each condition, it uses logical OR, which reads FTFL_FSTAT again, then writes it back.
The "write 1 to clear" approach is popular, because it offers 2 advantages:
1: Write-1-to-clear is an atomic operation. With the read-modify-write approach of logical OR, an interrupt can occur after the read instruction, or after the OR instruction. If the interrupt code also manipulates that register, when control returns, the code will write a stale value based on the read that occurred before the interrupt. This is the main reason why write-1-to-clear is so popular in hardware design.
2: Only writing is faster. Reading requires waiting for the peripheral bridge. Only writing allows the value to be written out to the peripheral bridge, which can complete the actual write to the hardware while the CPU moves on to the next instruction(s).
That entire block of code, which performs at least 3 peripheral reads, and as many as 6 reads and 3 writes, could be replaced by a single write, without ANY slow reads at all. There's no need to read the bits if your goal is only to clear them, and all 3 can be accomplished in a single bus cycle:
FTFL_FSTAT = FTFL_FSTAT_ACCERR_MASK | FTFL_FSTAT_FPVIOL_MASK | FTFL_FSTAT_RDCOLERR_MASK;
The write-1-to-clear feature is meant to enable this very efficient, inherently interrupt safe approach.
Sadly, many programmers are unaware of how to most effectively leverage the advanced features of the hardware.
