My CAN setup is written as below.
Call FLEXCAN_Enable(), FLEXCAN_EnterFreezeMode(), FLEXCAN_Init() in the CAN_Init() function.
I am not good at English. Thank you for your understanding.
status_t CAN_Init(can_instance_t instance, const can_user_config_t *config)
{
status_t status = STATUS_ERROR;
uint8_t index = 0;
/* Define CAN PAL over FLEXCAN */
#if (defined (CAN_OVER_FLEXCAN))
if ((uint8_t)instance <= FLEXCAN_HIGH_INDEX)
{
flexcan_user_config_t flexcanConfig;
/* Clear Rx FIFO state */
s_flexcanRxFifoState[instance].rxFifoEn = false;
/* Configure features implemented by PAL */
flexcanConfig.max_num_mb = config->maxBuffNum;
flexcanConfig.flexcanMode = (flexcan_operation_modes_t) config->mode;
flexcanConfig.fd_enable = config->enableFD;
flexcanConfig.payload = (flexcan_fd_payload_size_t) config->payloadSize;
flexcanConfig.bitrate.phaseSeg1 = config->nominalBitrate.phaseSeg1;
flexcanConfig.bitrate.phaseSeg2 = config->nominalBitrate.phaseSeg2;
flexcanConfig.bitrate.preDivider = config->nominalBitrate.preDivider;
flexcanConfig.bitrate.propSeg = config->nominalBitrate.propSeg;
flexcanConfig.bitrate.rJumpwidth = config->nominalBitrate.rJumpwidth;
flexcanConfig.bitrate_cbt.phaseSeg1 = config->dataBitrate.phaseSeg1;
flexcanConfig.bitrate_cbt.phaseSeg2 = config->dataBitrate.phaseSeg2;
flexcanConfig.bitrate_cbt.preDivider = config->dataBitrate.preDivider;
flexcanConfig.bitrate_cbt.propSeg = config->dataBitrate.propSeg;
flexcanConfig.bitrate_cbt.rJumpwidth = config->dataBitrate.rJumpwidth;
#if FEATURE_CAN_HAS_PE_CLKSRC_SELECT
flexcan_clk_source_t flexcanPEClkNames[FEATURE_CAN_PE_CLK_NUM] = FLEXCAN_PE_CLOCK_NAMES;
flexcanConfig.pe_clock = flexcanPEClkNames[0];
#endif
/* If extension is used, configure Rx FIFO */
if (config->extension != NULL)
{
flexcanConfig.is_rx_fifo_needed = true;
flexcanConfig.num_id_filters = ((extension_flexcan_rx_fifo_t *)
(config->extension))->numIdFilters;
flexcanConfig.rxFifoDMAChannel = 0U;
flexcanConfig.transfer_type = FLEXCAN_RXFIFO_USING_INTERRUPTS;
/* Compute maximum number of virtual buffers */
flexcanConfig.max_num_mb += CAN_GetVirtualBuffIdx(flexcanConfig.num_id_filters);
/* Update Rx FIFO state */
s_flexcanRxFifoState[instance].rxFifoEn = true;
s_flexcanRxFifoState[instance].numIdFilters = flexcanConfig.num_id_filters;
}
else
{
flexcanConfig.is_rx_fifo_needed = false;
flexcanConfig.num_id_filters = FLEXCAN_RX_FIFO_ID_FILTERS_8;
flexcanConfig.rxFifoDMAChannel = 0U;
flexcanConfig.transfer_type = FLEXCAN_RXFIFO_USING_INTERRUPTS;
}
/* Allocate one of the FLEXCAN state structure for this instance */
index = CAN_AllocateState(s_flexcanStateIsAllocated,
s_flexcanStateInstanceMapping,
instance,
NO_OF_FLEXCAN_INSTS_FOR_CAN);
/* Initialize FLEXCAN instance */
status = FLEXCAN_DRV_Init((uint8_t)instance, &s_flexcanState[index], &flexcanConfig);
/* Configure Rx FIFO if needed */
if ((status == STATUS_SUCCESS) && (s_flexcanRxFifoState[instance].rxFifoEn == true))
{
FLEXCAN_DRV_ConfigRxFifo(
(uint8_t) instance,
((extension_flexcan_rx_fifo_t *) (config->extension))->idFormat,
((extension_flexcan_rx_fifo_t *) (config->extension))->idFilterTable);
}
}
#endif
return status;
}
void FLEXCAN_Enable(CAN_Type * base)
{
/* Check for low power mode */
if(((base->MCR & CAN_MCR_LPMACK_MASK) >> CAN_MCR_LPMACK_SHIFT) == 1U)
{
/* Enable clock */
base->MCR = (base->MCR & ~CAN_MCR_MDIS_MASK) | CAN_MCR_MDIS(0U);
base->MCR = (base->MCR & ~CAN_MCR_FRZ_MASK) | CAN_MCR_FRZ(0U);
base->MCR = (base->MCR & ~CAN_MCR_HALT_MASK) | CAN_MCR_HALT(0U);
/* Wait until enabled */
while (((base->MCR & CAN_MCR_LPMACK_MASK) >> CAN_MCR_LPMACK_SHIFT) != 0U) {}
}
}
void FLEXCAN_EnterFreezeMode(CAN_Type * base)
{
base->MCR = (base->MCR & ~CAN_MCR_FRZ_MASK) | CAN_MCR_FRZ(1U);
base->MCR = (base->MCR & ~CAN_MCR_HALT_MASK) | CAN_MCR_HALT(1U);
/* Wait for entering the freeze mode */
while (((base->MCR & CAN_MCR_FRZACK_MASK) >> CAN_MCR_FRZACK_SHIFT) == 0U) {}
}
void FLEXCAN_Init(CAN_Type * base)
{
/* Reset the FLEXCAN */
base->MCR = (base->MCR & ~CAN_MCR_SOFTRST_MASK) | CAN_MCR_SOFTRST(1U);
/* Wait for reset cycle to complete */
while (((base->MCR & CAN_MCR_SOFTRST_MASK) >> CAN_MCR_SOFTRST_SHIFT) != 0U) {}
/* Clear FlexCAN memory */
FLEXCAN_ClearRAM(base);
/* Rx global mask*/
(base->RXMGMASK) = (((uint32_t)(((uint32_t)(CAN_RXMGMASK_MG_MASK)) << CAN_ID_EXT_SHIFT)) & (CAN_ID_STD_MASK | CAN_ID_EXT_MASK));
/* Rx reg 14 mask*/
(base->RX14MASK) = (((uint32_t)(((uint32_t)(CAN_RX14MASK_RX14M_MASK)) << CAN_ID_EXT_SHIFT)) & (CAN_ID_STD_MASK | CAN_ID_EXT_MASK));
/* Rx reg 15 mask*/
(base->RX15MASK) = (((uint32_t)(((uint32_t)(CAN_RX15MASK_RX15M_MASK)) << CAN_ID_EXT_SHIFT)) & (CAN_ID_STD_MASK | CAN_ID_EXT_MASK));
/* Disable all MB interrupts */
(base->IMASK1) = 0x0;
/* Clear all MB interrupt flags */
(base->IFLAG1) = CAN_IMASK1_BUF31TO0M_MASK;
#if FEATURE_CAN_MAX_MB_NUM > 32U
(base->IMASK2) = 0x0;
(base->IFLAG2) = CAN_IMASK2_BUF63TO32M_MASK;
#endif
#if FEATURE_CAN_MAX_MB_NUM > 64U
(base->IMASK3) = 0x0;
(base->IFLAG3) = CAN_IMASK3_BUF95TO64M_MASK;
#endif
}
