Standard DSC startup code most often includes a do loop. That do loop execution assigns a known value to the LA register. If you are using startup code that does NOT include a do loop, you need to explicitly initialize the LA register to an address that is not inside of an interrupt service routine. Why?  Standard save all and restore all code included by the IDE for interrupt handlers can itself be interrupted. There is a window of opportunity to be interrupted after the  restore all routine pushes the HWS (Hardware stack register) twice (thus setting both Loop flag in the SR and NL in the OMR registers). If you get interrupted just after doing the HWS pushes,  you can enter a fast ISR without clearing the LF, and then if your PC matches the uninitialized LA register (which aquires any possible value after power up) while in the middle of the interrupting ISR, then end of loop is recongnized and program flow becomes erratic after that.      Just initialize LA if you change the default stationery, please.   Depending on the version of IDE you are using, you may need to worry about the shadow register for M01 as well. Version 8.3 for DSC does not initialize this register, which can lead to issues. If you are using CW 10.6, the currently supported version, this register is initialized by default.   Please compare your start-up code to that produced by CW 10.6 for the part you are using if it fits this mask:  MC56F8xx, ..8xxx, ..8xxxx.

Based on customer requirement, I dragged the PMSM FOC control code here so that customer can download it from the link. BR Xiangjun Rong

Update for QuickStart GCT V2.6.3, Updates CPU peripherals and pinout page for all supported devices.

For switch mode power supply application, the output voltage resolution is dependent on PWM resolution, the PWM resolution is dependent on the PWM module driving clock(IP Bus clock) frequency and PWM signal output frequency.  But the eflexPWM module has a new feature Fraction Delay logic with Micro-Edge Placement, which is equivalent to increase the PWM module driving clock frequency, accordingly increase the PWM resolution. For the MC56F84xxx, there are two eFlexPWM modules: eFlexPWMA  and eFlexPWMB, the eFlexPWMA supports fractional Delay logic with micro-edge placement. For MC56F82xxx, there is only one eFlexPWMA module. The eFlexPWMA  module has an internal PLL which can multiply the PWM driving clock frequency by 32. For example, for the MC56F84789, the PWM driving clock frequency is 100MHz, the internal PLL of eFlexPWM module can output a clock frequency 32*100MHz=3.2GHz, so the PLL clock cycle is 312pS, in other words, the fractional cycle time of eFlexPWM is 312pS. For the eFlexPWM module, the eFlexPWMA_SM0 counter counts tick from the value of PWMA_SM0_INIT to  the value of PWMA_SM0VAL1 register, the main duty cycle of PWMA_A0 signal is controlled by PWMA_SM0VAL2(rising edge) and PWMA_SM0VAL3(falling edge), the main duty cycle of PWMA_B0 signal is controlled by PWMA_SM0VAL4(rising edge) and PWMA_SM0VAL5(falling edge). The new feature Fraction Delay logic with Micro-Edge Placement of eFlexPWM can place the rising or falling edge with fractional cycle time, which increase the PWM resolution by 5 bits. The demo code demonstrates the feature of Fraction Delay logic with Micro-Edge Placement  the eFlexPWM. The SM0 module outputs two channels PWMA_A0 and PWMA_B0. This is the configuration:for PWMA_SM0VAL2= PWMA_SM0VAL4=0xfffd, PWMA_SM0VAL3= PWMA_SM0VAL5=0x03, and PWMA_SM0CTRL2=0x2000; PWMA_SM0FRCTRL=0x8104; PWMA_SM0FRACVAL1= PWMA_SM0FRACVAL2= PWMA_SM0FRACVAL4= PWMA_SM0FRACVAL5=0x00; PWMA_SM0FRACVAL3=0xf000; From the above configuration, the PWMA_A0 and PWMA_B0 are in independent mode and the main duty cycle is the same. But PWMA_SM0FRACVAL3 is assigned with 0xF000, so the falling edge of PWMA_A0 will have a fractional placement as the following figure. The code is developed under CodeWarrior for microcontroller ver 10.6 and processor Expert, TWR-8200 board.   In the above figure, the there are two channels which are superimposed together so that user can compare the timing. The channel1(yellow trace) is the PWMA_A0 signal with a fractional edge placement which is connected to pin9 of J510 on TWR-8200 board. The Channel2(pink trace) is PWMA_B0, which does not have fractional edge placement and connected to pin11 of J510. BR XiangJun Rong Original Attachment has been moved to: HRpwm82748.rar