Hi, Padma,
For detailed information about the Asynchronous SRAM, pls refer to the Chapter 4
External Memory Interface (EMI).
Pls refer to the figure 4-3, you use 128K*16 bits SRAM, the memory address is from A0~A16, the A17~A23 are used to decode the /CS signal. I suppose for example, you use /CS2 for one 128K SRAM, /CS3 for another 128K SRAM.
1)For /CS1, you can use the address:
A23 A22 A21 A20 A19 A18 A17 A16.................
0 0 0 1 1 1 1
You can access the 0x00 0000 to 0x 1E 0000 as the /CS2 address
You can set the Chip Select Base Address Registers 2 as 0x1E05
For /CS2, you can use the address:
A23 A22 A21 A20 A19 A18 A17 A16.................
0 0 0 1 1 1 0
You can access the 0x00 0000 to 0x1C 0000 as the /CS3 address
You can set the Chip Select Base Address Registers 2 as 0x1C05
For the other register, you can set based on your requirement.
You can PE to set the EMI register.
Hope it can help you
BR
XiangJun Rong
