84789 DMA configuration - automatic SPI read

[TurboMan]

Firstly, I cannot find where to open a new service request for DSCs. More information would help here, thank you.

I have a DMA configuration issue with the MC84789VLL.

Here is what I wish to do with DMA:

1. Set up SPI transmit to automatically transmit 7 bytes (1st = address, 2-7 = 0xFF)

2. Configure receive DMA to transfer 7 bytes to a buffer in memory.

3. Trigger the transfer and deal with the data in memory when it has arrived.

4. I have partially managed this with a cycle-steal transfer triggering a 2nd DMA channel (with channel linking) to read back a byte each time.

My problems:

1. The DMADONE ISR handler is entered too early. I have to transfer 9 bytes so that chip select (managed manually) is triggered in the right place.

2. The returned data in the buffer is rubbish data. The oscilloscope says 0x00, 0x10, 0x00, 0x50... but the data buffer in memory will display 0xFF, 0xFF, 0x00, 0x00, 0x10, 0x10 and the rest at 0. It looks like a byte/word size issue but source, destination and SPI transfer size are all at byte settings. This happens on the first transfer, then all subsequent transfers just fill the buffer with 0x3Fs.

From paper specifications, I've said it's possible to do what I want above. Does anyone (NXP support?) have an example of the above? The awkward part is the first byte being different from the rest.

Help very much appreciated,

regards

[xiangjun_rong · Accepted solution]

Hi, Turboman,

Firstly, it seems you use the linked DMA channel to transfer data from SPI receiver data register to memory, I have checked the section 3.3.5.1 DMA channel assignments in the MC56F847xxRM, the SPI transmitter and receiver have it's own DMA channels. For example channel 2 in DMA0 is "SPI0 Receiver Full", channel2 in DMA1 is "SPI0 Transmitter Empty", in other words, you can use DMA0 to transfer from SPI0 receiver to memory, while use DMA1 to transfer from memory to SPI0 transmitter data register.

Secondly, the source/destination register should be Btye address, in other words, the actual register should be left shift one bit:

DMA_SAR1=(long)&array[0]<<1;

  DMA_DAR1=(long)FQSPI0_SPDTR<<1;

I have developed an example, but it is not fully tested, pls refer to it.

BTW, there is a note about the SPI plus DMA, it says "Restriction: Do not use CPHA = 0 while in DMA mode.", pls refer to the CPHA bit explanation in section 36.3.1 SPI Status and Control Register (QSPIx_SPSCR).

Clock Phase:

This read/write bit controls the timing relationship between the serial clock and SPI data. To transmit data

between SPI modules, the SPI modules must have identical CPHA values. When CPHA = 0, the SS_B pin

of the slave SPI module must be set to 1 between data words. To set SSB to 1 between data words when

SSB_AUTO is 1, set SSB_STRB to 1.

Restriction: Do not use CPHA = 0 while in DMA mode.

In conclusion, pls use two DMA channels, set CPHA bit if possible. If you still have issue, pls update the case, I will test on my board.

BR

XiangJun Rong

[TurboMan]

Hello Xiangjun,

  thanks for your prompt response, and further information. I resolved the issue this morning, and found it was due to linking the two channels. Doing this will replicate(repeat) the transfer I wanted (when choosing <01> as the linking option) and so keeping the DMA configuration but without linking has solved this issue for me. You're correct, I'm using 2 DMA channels, 0 and 1, as I'm dependent on SPI1 transmit empty and SPI1 receive full flags for DMA handling.

Thank you again,

Best Regards